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PWM frequency and duty cycle reloading

Other Parts Discussed in Thread: CONTROLSUITE

I have some problems with reloading PWM frequency and duty cycles without causing any glitches in the signals on a 28032 part.

I have an interrupt that calculates a new  frequency and duty cycles for all my PWMs at a 100kHz rate. The interrupt is not run in synchronization with the frequency on the PWMs,  and the PWM frequency is varied in a range higher than the interrupt frequency. When I reload the PWM frequency and duty cycles I sometimes observe that some of the signals deviate from the frequency or duty cycle that I reloaded. Since the interrupt frequency and PWM frequency is not synchronized I cannot always guarantee that I reload all the PWMs prior to period or zero (center-aligned counters). I control the period, duty cycle and deadband on eight PWMs and my reload routine requires quite a few cycles.

So my question is how can I guarantee that reloading does not cause glitching? I have worked with MCUs where it was possible to write to a load register (after reloading all the shadow registers) which activated a reload at the next period or zero from shadow. I haven't found a similar mechanism in C2000.

Do any of you have any ideas/experience on how to solve this problem?

Thanks.

 

  • Hi Stian,


    Piccolo has shadow registers too. Check out section 2.2.3.1 in the document http://www.ti.com/litv/pdf/spruge9d

    Best regards

    Andreas

  • Thanks for your answer.

    I have configured all my PWMs to use shadow registers. Even though I use shadow registers the problem persists.

    If I want all my PWMs to update period, duty cycle and deadband at a period or zero counter match, I must ensure that I have written to all shadow registers between zero-period or between period-zero. I don't believe I can guarantee this since my PWM frequency is off-sync with the 100kHz ISR. The effect of this is that occasionally my ISR will update the shadow registers whilst the PWM counters cross period or zero. The effect of this is that a subset of my PWMs reload at period or zero, and the remaining set is delayed by half a period.

    The ideal case would be to run the ISR at the PWM frequency, but this is way too resource intensive.

  • I am not sure how it is creating glitches .. with the available shadow regsiters it is not likely to experience glitches .. your ePWM should load only once from your shadow register at period or counter zero or both depedning on your configuration... since your duty cycle calculation routine is not synchronized with PWM frequency you may get multiple writes to your shadow register but that shouldn't affect your loading ... I am assuming you are calculating your duty ratio as a percentage of your period value so that the duty ratio can never be greater than the period...

  • Here's an example (assuming PWM1, 2, 3 and 4 counters are synchronized):

    * Enter 100kHz interrupt
    * Calculate frequency, duty cycle and deadband
    * Update PWM1A/B by writing to shadow registers
    * UpdatePWM2A/B by writing to shadow registers

    At this time the PWM counters cross period (at which PWM1A/B and PWM2A/B reloads)

    * Update PWM3A/B by writing to shadow registers     <----- PWM3A/B are updated at zero-crossing!
    * Update PWM4A/B by writing to shadow registers     <----- PWM4A/B are updated at zero-crossing!
    * Exit 100kHz interrupt

    The problem here is that PWM1, 2, 3 and 4 are not reloaded at the same point. Perhaps the description 'glitch' is incorrect, but the above scenario should cause an inconsistent reload.

  • Stian,

    are you using HR mode?

    the only way to guarantee this is to have an ISR update the period and cmpa value, there can be a workaround possible depending on if you are using HR mode or not..?

    Regards

    Manish Bhardwaj

  • Manish,

    I have enabled HR mode to control the period on all PWMs.

  • Stian,

    There is an example in the device header files for the hr pwm, it uses an ISR update for multiple PWM's.

    It can be found at

    controlSUITE\device_support\f2803x\v123\DSP2803x_examples_ccsv4\hrpwm_mult_ch_prdupdown_sfo_v6

    However there is a caveat while using multiple PWM's in HR Mode which is discusses on the following thread,

    http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/62564/224715.aspx#224715

     

    Regards

    Manish Bhardwaj

  • Manish,

    Thanks for the project reference. I'll look into it. I was under the impression that a reload ISR was the only solution to this problem.

  • Stian,

    You are correct  reload ISR is the only option, the example uses a reload ISR, however as the frequencies go higher and higher reload ISR does not remain and option depending on how many cycles would you have to update the registers.  What can be done is  slow down the interrupts , you can configure registers such that interrupt is only issues every alternate PWM cycle.  This would reduce the ISR burden significantly.

    Also if you have PWM spare's you can use a multiple of the frequency on this PWM, to reduce the ISR burden and sync it with the other PWM's.

    regards

    Manish Bhardwaj

  • What device are you trying to use?

  • I'm using 28035 at the moment, but the plan is to use 28032 later in the project. An option might be to stay with the 28035 and use the CLA for reloading. The maximum PWM frequency might touch 300kHz and reloading 4 PWM packages with duty cycles, frequency and db requires quite a few cycles.