I'm having some trouble with the CPU and Instruction Set Reference guide for the C28xx.
Page 96 of the TMS320C28xx CPU and Instruction Set Reference Guide describes *BR0--,ARPn indirect address mode. But the example below seems to have some contradictions. The example indicates a post-increment in the comments, but I assume it should be decrement. The comment says "post−increment XAR3 with AR0 reverse borrow substract". Assuming decrement, does this mean decrement XAR3 after it is loaded with ACC, and then perform the subtraction. Or is the -- decrement being done by the subtraction? The top of the page seems to indicate the latter, but the comments in the example indicate the former. With the errors and ambiguity it is making it a little too confusing for me to be certain.
I have found multiple references where -- is called an increment in the indirect address section. There were enough I wondered if it was some underscore that indicated increment. This guild has dozens of other typographical errors that change meanings. A couple samples:
Page 78:
Example 1 shows a read of a non-protected following a write from protected as pipeline protection (3) while Example 2 shows the same read of non-protected following a write from protected as no protection. I assume one must be wrong, but I'm not sure which.
Page 89 lower example:
MOVL XAR2,#Array1 ; Load XAR2 with start address of Array1
MOVL XAR2,#Array2 ; Load XAR3 with start address of Array2
The actual code overwrites XAR2 with the address of Array 2.
In general, I have been able to decipher the intent through the errors, but is there a better copy that has been proofed? I pulled this from the TI website a couple of days ago. The last revisions were made May 2015. It is frustrating to try to learn a new processor with such a mature document that is used for the entire C2000 line and have these types of errors. I'm hoping I am simply using one that is out of date.
Example (s):
; Transfer contents of Array1 to Array2 in bit reverse order:
MOVL XAR2,#Array1+(N-1)*2 ; Load XAR2 with start address of Array1
MOVL XAR3,#Array2+(N-1)*2 ; Load XAR3 with start address of Array2
MOV @AR0 #N ; Load AR0 with size of array,
; N must be a multiple of 2 (2, 4, 8, 16,...)
MOV @AR1, #N-1 ; Load AR1 with loop count N
NOP *,ARP2 ; Set ARP pointer to point to XAR2
SETC AMODE ; Make sure AMODE = 1
.lp_amode ; Tell assembler that AMODE = 1
Loop:
MOVL ACC,*--,ARP3 ; Load ACC with location pointed to by XAR2,
; post-increment XAR2, set ARP pointer to point to XAR3
MOVL *++,ACC,ARP1 ; Store ACC with location pointed to by XAR3,
; post−increment XAR3, set ARP pointer to point tp XAR1
MOVL *BR0--,ACC,ARP1 ; Store ACC with location pointed to by XAR3,
; post−increment XAR3 with AR0 reverse borrow substract,
; set ARP pointer to point to XAR1
XBANZ Loop, *--,ARP2 ; Loop until AR1 == 0, post−decrement AR1,
; set ARP to point to XAR2
