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Hi expert,
The reset source table on TRM and DS are different, could you let me know why? (JTAG/DEBUG... column)
BTW, could you let me know what "JTAG/DEBUG Logic Reset" means here?
Does BOR reset belongs to the POR?
Thanks
Sheldon
Hi Sheldon,
Table 5-9 is correct. I'll provide this feedback to our team.
BTW, could you let me know what "JTAG/DEBUG Logic Reset" means here?
JTAG/DEBUG Logic reset means emulation related logic will get reset which means JTAG (CCS) connection will be broken.
Does BOR reset belongs to the POR?
Yes.
Regards,
Vivek Singh