Hi all,
I am using three pwm modules and I configured pwm1 as master and pwm 2&3 as slave.I want to change the phase of pwm 2&3 (0 to 180 degree) with respect to pwm 1.
I am dont know how to sync three pwm modules and I am not understanding from datasheet also.
Below is snippet of my code:
void
InitEPwm1()
{
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm1Regs.TBPRD = 300; // Set timer period( for 100 khz)
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//
// Setup shadow register load on ZERO
//
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Set Compare values
//
EPwm1Regs.CMPA.half.CMPA = 150; // Set compare A value
// EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, up count
// DEAD TIME
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_DB;
EPwm1Regs.DBFED = EPWM1_DB;
}
//
// InitEPwm2Example -
//
void
InitEPwm2()
{
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down
EPwm2Regs.TBPRD = 300; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300; // set Phase for 180 degree
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN ;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN ;
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//
// Setup shadow register load on ZERO
//
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Set Compare values
//
EPwm2Regs.CMPA.half.CMPA = 150; // Set compare A value
// EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM2A on Period
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Set PWM2A on event A, up count
// EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Clear PWM2B on Period
// EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; // Set PWM2B on event B, up count
// DEAD TIME
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED = EPWM2_DB;
EPwm2Regs.DBFED = EPWM2_DB;
}
void
InitEPwm3(void)
{
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down
EPwm3Regs.TBPRD = 300; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = 300; // set Phase for 180 degree
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP ;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
//
// Setup shadow register load on ZERO
//
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Set Compare values
//
EPwm3Regs.CMPA.half.CMPA =150 // Set compare A value
EPwm3Regs.CMPB = 150 // Set Compare B value
//
// Set Actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on period
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM3A on event B, down count
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM3A on period
EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM3A on event A, up count
}
But for this code only pwm 2 is phase shifted for 180 degree,pwm 3 is not phase shifting. My TBCLK=SYSCLCK=60MHZ.
please give me a solution.
Thanks,
Aslam
voidInitEPwm1_lag(){ // // Setup TBCLK // EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0 EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; EPwm1Regs.TBCTR = 0x0000; // Clear counter EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadow register load on ZERO // EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set Compare values // EPwm1Regs.CMPA.half.CMPA = EPWM1_CMPA; // Set compare A value // EPwm1Regs.CMPB = EPWM1_MIN_CMPB; // Set Compare B value
// // Set actions // EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM1A on event A, up count
// EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1B on Zero // EPwm1Regs.AQCTLB.bit.CAD = AQ_SET; // Clear PWM1B on event B, up count
// DEAD TIME
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm1Regs.DBRED = EPWM1_DB; EPwm1Regs.DBFED = EPWM1_DB;
}
//// InitEPwm2Example -//voidInitEPwm2_lead(){ // // Setup TBCLK // EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up down EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period
EPwm2Regs.TBPHS.half.TBPHS = inverter_phase(0.1); // set Phase EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm2Regs.TBCTL.bit.PHSDIR = TB_DOWN ; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN ;
EPwm2Regs.TBCTR = 0x0000; // Clear counter EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadow register load on ZERO // EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set Compare values // EPwm2Regs.CMPA.half.CMPA = EPWM2_CMPA; // Set compare A value// EPwm2Regs.CMPB = EPWM2_MAX_CMPB; // Set Compare B value
// // Set actions //
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Clear PWM2A on Period EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Set PWM2A on event A, up count
// EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Clear PWM2B on Period // EPwm2Regs.AQCTLB.bit.CAD = AQ_SET; // Set PWM2B on event B, up count
// DEAD TIME
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL; EPwm2Regs.DBRED = EPWM2_DB; EPwm2Regs.DBFED = EPWM2_DB;
}
voidInitEPwm3_rectifier(void){
// // Setup TBCLK // EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up/down EPwm3Regs.TBPRD = 150; // Set timer period/* EPwm2Regs.TBPHS.half.TBPHS = 0;//inverter_phase(0.4); // set Phase EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP ; EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;*/ EPwm3Regs.TBCTR = 0x0000; // Clear counter EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV2; // Clock ratio to SYSCLKOUT EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// // Setup shadow register load on ZERO //
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW; EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// // Set Compare values // EPwm3Regs.CMPA.half.CMPA =75; //Duty_Rectifier(0.94); // Set compare A value EPwm3Regs.CMPB = Duty_Rectifier(0.05); // Set Compare B value
// // Set Actions // EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on period EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR; // Clear PWM3A on event B, down count
EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR; // Clear PWM3A on period EPwm3Regs.AQCTLB.bit.CBD = AQ_SET; // Set PWM3A on event A, up count
}
