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TMS320F28379D: SPI ON CPU 2 with manual and non manual SPISTE

Part Number: TMS320F28379D

Hello,

I have a project that uses SPI and I am in the process of migrating it to CPU2.

My program requires manual and automatic operation of the SPI enable bit.

GPIO_66_SPISTEB in this case, Previously my project would have it running automatic, but for bulk reads over the size of the fifo buffer I have manually been setting it.

However in CPU2 the pin no longer goes low, I assume this line is not functioning correctly on CPU2

I call this before setting it low for long read/writes
GPIO_setPinConfig(GPIO_66_GPIO66); 

GPIO_writePin(66, 0);


And then set it back to 

GPIO_setPinConfig(GPIO_66_SPISTEB);

My question is should this work on CPU2? I followed the examples and use this to pass control.

SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 2, SYSCTL_CPUSEL_CPU2);

GPIO_setMasterCore(66, GPIO_CORE_CPU2);



Also is there a better way to control the enable pin other than through setting a GPIO?


Any help would be appreciated.

Cheers

  • Chris,

    I believe the below code is being executed from CPU1 and CPU2 as shown below. Am I correct?

    CPU1 side code:

    GPIO_setMasterCore(66, GPIO_CORE_CPU2);

    CPU2 side code:

    GPIO_setPinConfig(GPIO_66_GPIO66); GPIO_setDirectionMode(66, GPIO_DIR_MODE_OUT);

    GPIO_writePin(66, 0);

    GPIO_setPinConfig(GPIO_66_SPISTEB);

    When you trying to use GPIO66 as GPIO output pin, then you need to configure GPIO66 as both GPIO pin and output pin. From the code snippet, I don't the configuration for GPIO66 to be configured as output pin from CPU2 side code. I have shown how you need to configure GPIO66 as output pin with code statement highlighted in yellow.

    When you trying to use GPIO66 as SPISTEB pin, then SPI peripheral automatically controls SPISTEB. So, you don't need any other additional configuration other than GPIO_setPinConfig(GPIO_66_SPISTEB);

    Regards,

    Manoj

  • Is this issue resolved?