Other Parts Discussed in Thread: TMS320F28377D
Hi Team,
This is customer request, I would be very happy if you can support.
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1-Can Error pin of ESM set as both active low or active high?
2-Are there Altium and Mentor PADS simulation models available for Hercules and C2000 series?
3-Is there a need for SRAM with C2000 series MCUs?
4-We would like to configure C2000 I/Os as logic gates to simulate gate logic on a FPGA. From the datasheet it is done via X-BAR connected LUTs and I/Os. We know that LUTs have different operation characteristics than FPGA gates(propagation delay/uncertain output by sending to RAM which is called LUT glitch) How can C2000 prevent that glitch to be safe and also does it provide asynchronous logic I/O mechanism?
5-Hercules series MCUs switch to internal clock when the external clock fails. How could two Hercules be synchronized in case of their external clock failure?
6-For C2000 how can we configure CLB mechanism? Is there a specific tool for different IDEs except CCS?
7-How many logic gates can be implemented on C2000 series MCUs?
8-What type of core C2000 include? (Any further information would be great)
9- Is there any other mcu solution for implementing logic gates with the same performance as in FPGAs?
10-Some of the C2000 MCUs defined as functional safety compliant? Does it apply for the all types of fields(such as using household compliant product in automotive field(if both of them are functional safety compliant ))
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Thanks in advance
