TMS320F280049C: Motor RDK EPWM configuration

Only need COMPARE_A for PWM output since the dead band is enabled in these labs. COMPARE_C is used to generate the event for ADC trigger and set a fixed value in all labs except the lab needs over modulation.

The three EWPM modules for three-phase inverter are synchronized by enabling the ePWM module time base clock sync signal.

You might take a look at the technical Reference Manual (SPRUI33B) about EPWM, which has a very detailed description of using the EPWM.

Yanming Luo said:

Only need COMPARE_A for PWM output

And that is not how the SDK triggers SOC regardless of dead band.

Yanming Luo said:

The three EWPM modules for three-phase inverter are synchronized by enabling the ePWM module time base clock sync signal.

Yet the FOC phase drive inverter outputs are 120° apart. So it seems odd _C was chosen versus _D, since _C will set a 60° -90°advanced SOC trigger action and comp_C was not being used for inverter PWM generator (gen). It seems an mistake or assumption gen-C was being used for PWM when actually gen-D was specified. The order is A-D-B into inverter 1/2 bridge drivers. Typical gen progressions are A-B-D to account for GPIO routing into a gate drive. So A-D-B makes no sense either unless ROM calls to FAST expect reversed gen order and that is not disclosed in any x49c MCU documentation.

The generators are spaced evenly (synchronized) they do not set ADC triggers at the same rotor angle or at the same time, only counting updates (duty cycle) are applied synchronously. That is how SW can add time delay to SOC by selecting lower gen comparator action to trigger ADC. Typical order of phase angle commutation cascades downward,e.g. gen A->B->C->D each have a different SOC trigger point relationship. That is relative to individual comparator action event timing, in this case of SOC.

I remain concerned of rotor vibration small PM motor ID lab 5 end of (LC). This vibration seems more SW related in my opinion! Something in PWM timing loop makes odd stator imbalance and rotor shakes in a bad way. 

Yanming Luo said:

COMPARE_C is used to generate the event for ADC trigger

How was COMPARE_C period being loaded via SW is the real question. I see how _A load count center but _C was never being set a trigger event or included in duty cycle updates. It seems _A is the only compare action being enabled for shadow updates.

Might the FAST estimator work better if SOC was kept synchronous to PWM voltage changes each 32µs mainISR()? The way it was configured, _C triggering SOC every 5 TBCTR clock ticks (50ns)? Yet EOC interrupt remain somewhat synchronous to voltage changes in each Uout sector but...

Over triggering SOC seems to explain how the rotation angle in motor ID and LC becomes partially out of phase with current angle. The rotor thus vibrates from poorly formed commutation angles in LC mode. The EOC samples triggered interrupts easily over runs mainISR(). It seems the mainISR() GPIO might fires several times in the short period edges on either side of any 50µs period. Oddly decimation over run appears random to the human eye, rapid changes of TBCTR (100Mhz) directly triggering EOC interrupts, 50ns intervals. Again it seems SW is more likely to blame for rotor vibration than hardware.

        // setup the Counter-Compare Control Register (CMPCTL)
        EPWM_setCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                             EPWM_COUNTER_COMPARE_A,
                                             EPWM_COMP_LOAD_ON_CNTR_ZERO);
        //
        EPWM_disableCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                             EPWM_COUNTER_COMPARE_B);

        // Not used
        EPWM_disableCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                             EPWM_COUNTER_COMPARE_C);

        //
        EPWM_disableCounterCompareShadowLoadMode(obj->pwmHandle[cnt],
                                             EPWM_COUNTER_COMPARE_D);

        // setup the Action-Qualifier Output A Register (AQCTLA)
        EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                      EPWM_AQ_OUTPUT_A,
                                      EPWM_AQ_OUTPUT_HIGH,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
		//
        EPWM_setActionQualifierAction(obj->pwmHandle[cnt],
                                      EPWM_AQ_OUTPUT_A,
                                      EPWM_AQ_OUTPUT_LOW,
                                      EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);

Yanming Luo said:

COMPARE_C is used to generate the event for ADC trigger and set a fixed value in all labs except the lab needs over modulation.

I see the fixed value 5 was set and still makes no sense how that relates to Id/Vd samples when the generator shadow mode update was disabled.  Seemingly FAST would produce better results to use last generator D every 360° cycle, 90° angle. The #5 seems to represent TBCTR clock ticks not being exactly synchronous to rotor commutation periods.  At least _C is close to _D but still triggers advanced SOC window by some number of electrical degrees prior to _D compare functions.

It's odd you should mention over modulation lab since the inverter wave form in lab 5 appears more trapezoidal shape than sinusoidal. 

You have not yet answered why Comp_D (generator D) was not used to trigger SOC versus Comp_C, explanation was vague. Might a better SOC window occur via Comp_D? Assuming Comp_A compare somehow synchronizes Comp_C trigger events (50µs) seems a far reach. Perhaps if shadow mode was enabled the updates would maintain global synchronization? It seems there is no global synchronization between all generators if only A shadow and B, C, D are disabled.

How does it make sense to use Comp_C that never compares up/down counts relative to other 50µs periods? The TBCTR time base is 100Mhz (10ns), Comp_C seemingly is not triggering SOC @50µs as one might expect it to. Perhaps triggering SOC @50ns cause interrupt over runs. Even if not over run how are global synchronous updates ever going to occur with shadow disabled, Gen B,C,D? TRM seems to infer global synchronous updates occur via shadow mode. I can only say other PWM modules require global synchronous updates to be enabled at the CTRL register level for all generators, not just Gen A.

BTW: On our other ePWM (TI) dead band occurs and is configured for local generator updates mode. Dead band is not part of the global synchronous updates to generators. One would assume x49c ePWM version 4 has the same ability to set dead band updates local sync, global sync or no sync (immediate). 

Customer might expect SDK labs to portray proper ePWM module configuration for use in production firmware. With 6 step this is a bit more flexible but space vector ROM calls complicates the schema.

Hi Yanming,

Recently verify PWM generator order from J6 header into BoostXL-drv8320 and generator D was put to center, A,D,B. The order baffles how modulation drives are kept 60° overlap. Our other MCU modules  PWM generators order (A, B, C) to achieve proper FOC 120° phases. We can not arbitrarily switch generator order without some kind of impact to commutation, e.g. A,C,B. However we can reverse EMF zero crossing order (C,B,A) for reversing the motor direction. 

Does SDK Clarke or ADC read data modules switch phase order back to A,B,D to account for odd generator order A,D,B? if so it should be well noted (hal.c) that was done as a counter measure.

One might get the impression that is the primary way how to produce DSP 3 phase sinusoidal waveforms. Versus leveraging EPWM module Sync control register points between 3 generators. I don't find SW controls Lab5 for EPWM module Sync register or how it is updated by FAST estimator theta angle out data on left side (Fig.1-3) SPRUHJ1H–January 2013–Revised June 2019.

The only FAST angle control is being hot injected into Clarke Park/Inv without any regard for HW commutation phase angles. That perhaps explains the vibrating Nidec motor rotor that also burned out. A second brand new Nidec vibrated equally as much. Forcing the user Speed Hz during ramp up into LC and that once locked the rotor but seemed to produce less vibration for EST Online.   

Gl said:

So it seems odd _C was chosen versus _D, since _C will set a 60° -90°advanced SOC trigger action and comp_C was not being used for inverter PWM generator (gen).

CCS debug confirms there is ZERO count action PWM generator _COMPC but is action on _COMPD. Seemingly leads to puzzle how theta angle of FAST estimator ever updates PWM sync control register. Perhaps ePWM might produce a pristine sinusoidal current wave form had the sync control register been include LAB5?