TMS320F28379D: Propagation delay when the CLB absorbed a simple gate logic.

Hideaki Nambu

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE, LAUNCHXL-F28379D, SN74HC08

Hello,

Could you please advise the propagation delay when the CLB absorbed a gate logic like an AND gate?

My idea would be like, a couple of EPWM clocks, but a better advice is highly appreciated.

I asked this because the delay of the CLB AND gate changed by the PLL setting. I thought the CLB logic could not be asynchronous, then we would like to have an explanation about the timing specification, something different form the 74xx logic parts.

I tried the sample code 8:
C:\ti\c2000\C2000Ware_2_01_00_00\driverlib\f2837xd\examples\cpu1\clb\clb_ex8_external_signal_AND_gate.c

over 5 years ago

0 Subrahmanya over 5 years ago

TI__Mastermind 24095 points

Hi,

Can you clarify what exactly is your observation in terms of the delay change w.r.t. PLL settings?
CLB is not completely asynchronous though you are using only AND gate function.
Have you enabled synchronizers on the inputs either in GPIO or CLB?

0 Hideaki Nambu over 5 years ago in reply to Subrahmanya

Mastermind 9165 points

Subrahmanya,

Thank you for your response.

When I configured GPAQSEL1.GPIO0=3(Asynchronous), the propagation delay was approx. 20ns regardless the symbol “_LAUNCHXL_F28379D” was defined or not.

Therefore my test result was approx 20nsec, on the other hand, is there TI's spec ?

Anyway I would share my test result.

Sample code:

C:\ti\c2000\C2000Ware_2_01_00_00\driverlib\f2837xd\examples\cpu1\clb\clb_ex8_external_signal_AND_gate.c

Board:

LAUNCHXL-F28379D

Oscilloscope plots:

Ch1: J4-40 = GPIO0 = One of inputs to CLB AND2 gate. Signal from square waveform.

Ch2: J4-39 = GPIO1 = One of inputs to CLB AND2 gate. Tied to High.

Ch3: J4-34 = GPIO24 = Output of CLB AND2 gate. The plots show propagation delays.

[1-1]

Original code, _LAUNCHXL_F28379D defined.

3034.ex8_GPAQSEL1_GPIO0_0_200MHz.TIF

[1-2]

Modified code (GPAQSEL1.GPIO0=3(Asynchronous)), _LAUNCHXL_F28379D UNdefined.

7827.ex8_GPAQSEL1_GPIO0_0_100MHz.TIF

[2-1]

Modified code (GPAQSEL1.GPIO0=3(Asynchronous)), _LAUNCHXL_F28379D defined.

ex8_GPAQSEL1_GPIO0_3_200MHz.TIF

[2-2]

Original code, _LAUNCHXL_F28379D UNdefined.

ex8_GPAQSEL1_GPIO0_3_100MHz.TIF

0 Nima Eskandari over 5 years ago in reply to Hideaki Nambu

TI__Guru 52040 points

Are you saying that the delays are inconsistent?

0 Hideaki Nambu over 5 years ago in reply to Nima Eskandari

Mastermind 9165 points

Nima,

Thank you for your comment.

I was saying this at the beginning. But after I configured GPAQSEL1.GPIO0=3(Asynchronous), the propagation delay in my test got constant. It is approx. 20nsec.

I'm afraid that our customers would ask the propagation delays if we suggest to absorb logics into C2000 CLB. For example TI's SN74HC08 datasheet page-7 tells like tpd = 50nsec typical.

http://www.ti.com/lit/ds/symlink/sn74hc08.pdf

Therefore I would ask your advice if our customer asked propagation delay of, for example, an AND gate in the CLB.

0 Nima Eskandari over 5 years ago in reply to Hideaki Nambu

TI__Guru 52040 points

I dont think the propagation delays without the the synchronization is characterized.

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TMS320F28379D: Propagation delay when the CLB absorbed a simple gate logic.