TMS320F280049C: J7-Site2 pins PGA's

I just see drv8320rs user guide Table 3 and site 2 Pin Mux card (PGA2, PGA4, PGA6) but (hal.c) has (PGA1, PGA2, PGA4) configured for site 2. This become a problem when trying to convert pins for another DC inverter. The Launch Pad Pin Mux card and BoostXL-DRV8320RS user guide SPRUIJ3A–November 2018–Revised August 2019 seems a bit useless for that purpose unless it is correct and the SDK code is incorrect.

According to PinMux card PGA6 assigns ADCINC5 and PGA1 A3 has no ADC input pin on J7, TRM table 12-1. Contention exists A3, C5, C0, A9 in the documentation, PinMux and hal.c. Most confusing how SOC was configured since PGAn outputs go into the same ADC's Fig.12-4. Since Table 21-1 indicates PGA1, PGA2 are non-inverting inputs (only) MCU pins 18, 30 respectively, how can they also trigger SOC as configured below?

So is it PAG1 or PGA6? "will the real PGA please stand up"...

// configure the SOCs for hvkit_rev1p1
    // ISENA - PGA2->B9->RB0
    ADC_setupSOC(obj->adcHandle[1], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN9, HAL_ADC_SAMPLE_WINDOW); 

    // ISENB - PGA4->A15->RA0
    ADC_setupSOC(obj->adcHandle[0], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN15, HAL_ADC_SAMPLE_WINDOW); //ADC_CH_ADCIN3

    // ISENC - PGA1->C9->RC0 Or is it PGA6->C5
    ADC_setupSOC(obj->adcHandle[2], ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN9, HAL_ADC_SAMPLE_WINDOW); //ADC_CH_ADCIN5

The original desire was to use 3 external current monitor inputs into x49c J7 header pins, bypass 3 PGA's and retain 3x CCMPS. Oddly the separate SOC configuration ADCINxn hijacks pins needed (PAG2_OF, PAG4_OF, PAG6_OF) or is that PAG1_OF?  

Anyway J7 pins limit testing of external monitors unless PGAn are made non-inverting buffers for the external monitors.  

Table 12-1 seems to indicate SOC analog triggers were configured for the wrong pins on launch pad header (J7) PGA2, PAG4, PAG6. Notice PGA1 can't trigger C0 on J7 MUC pin 19 so it must be PGA6 (C5) and ADCIN5 for SOC trigger source. Also PGA2 PinMux input can't trigger C1, MCU pin 29 is not connected to J7 and PGA2 suffers same issue. It would seem the SOC trigger sources above post should come from PGA outputs and not via MCU pins. How on earth is that even working since PGA1/2 can only assign as Non-Inverting amplifier inputs?

Note: PGA4, PGA6 MCU pins 28/31 (C3/C5) respectively are the only shared ADCIN pins existing J7 according to table 21-1 or PinMux card.

The CMSS input Mux shown Fig.12-4 page 1453 is not shown in the CMSS  block diagram.  

The Mux selection was not documented but infers PGA6 (Not PGA1) and PGA's outputs do drive analog subsection input Mux. So the MCU pins are not all shared C1 A3 (pin 29 69) is missing into ADC and as configured for ISEN-A,B,C above site 2 booster pack headers.   

User guide does not mention the ADC inputs were shared via several external 0R added, no foot note on PinMux or Schematic. User guide assumes the reader to know removal of filter 0R on J7 is connected to ADCINx of other MCU pins. A reader naturally assumes J7 0R are connected as filter components of PGAx but not (Alternate) ADCINx.  

Why 3 ADC's and Table 21-1 inputs did TI engineers add 0R jumpers between ADC inputs? Now we know PGA input noise can come in from externally shared ADC channels, antenna loops. Disconnect PGA's to have external current monitors shown below and retain the CMSS trip zones into ePWM sub module. 

    // configure the SOCs for hvkit_rev1p1
    // ISENC - PGA2->A3->RA0       PGA2->B9->RC0
    ADC_setupSOC(ADCA_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN3, HAL_ADC_SAMPLE_WINDOW); // ADC_CH_ADCINA B9 obj->adcHandle[1]

    // ISENB - PGA6->C5->RC0       PGA6->A15->RB0
    ADC_setupSOC(ADCC_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN5, HAL_ADC_SAMPLE_WINDOW);// ADC_CH_ADCIN A15 obj->adcHandle[0]

    // ISENA - PGA4->C3->RC0       PGA4->C9->RA0
    ADC_setupSOC(ADCC_BASE, ADC_SOC_NUMBER0, ADC_TRIGGER_EPWM1_SOCA,
                 ADC_CH_ADCIN3, HAL_ADC_SAMPLE_WINDOW);  // ADC_CH_ADCIN C9 obj->adcHandle[2]

    /* Gx_ADCA3/P21 AG1 drives CMPSS1 input Mux HP/LP3 */
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_1, 3); //PGA2,4
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_1, 3); //PGA2,4

    /* GxADCC3/P41 AG2 drives CMPSS2 input Mux HP/LP4 */
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_4, 1); //PGA4,4
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_4, 1); //PGA4,4

    /* Gx_ADCC5/P61 AG2 drives CMPSS6 input Mux HP/LP4 */
    ASysCtl_selectCMPHPMux(ASYSCTL_CMPHPMUX_SELECT_6, 1); //PGA6,4
    ASysCtl_selectCMPLPMux(ASYSCTL_CMPLPMUX_SELECT_6, 1); //PGA6,4

Kevin Allen18 said:

LaunchPad to provide multiple options / uses at the pin

I use it all the time but was confused by the PinMap card and this general statement you again choose to use was meaningless without scope. There should be a note explaining 0R resistors were used to bridge multiple analog inputs on J7. I was aware of the filter and need to remove 0R but there was no mention of why that was necessary, anyone assume required to use the filter.

Unless one reviews schematic J7 several times then switches to page U1C far right side 0R are shown. It never clicked to look to the right side of U1C so I was unaware why 0R were placed there to begin with and the programmers mistake compounded confusion. It seems unnecessary to bridge analog input pins when there are 3 ADC's shared among MCU pins internally. Another point being other TI launch pads do NOT bridge analog inputs and provide an external header. It seems 0R analog bridges and parallel traces into the ADC also violate best practice guidelines for signal input sources.   

Again 0R analog input bridges should not be necessary according to table 21-1.

GI,

This is documented in section 2.1.10 of the LP User's Guide: https://www.ti.com/lit/spruii7

Best,

Kevin

How does that explain in English (multiple) MCU pins were bridged together or (shared). Without an illustration to explain such was done text alone is meaningless even after review TRM Fig.12-4. I see this same note before and after reviewing Fig.12-4 but think 0R some how represent Rgnd show in illustration. The PGA has a connected ADC input so it makes no sense without illustration, word (Alternate/Shared) channel input was again left out. Perhaps the use of a few more adjectives to describe what, where, and why could help readers to better comprehend?

The note makes it seem to NEW kit reader, in order to use PGA filters option the 0R (Rgnd) Fig 14-1 has to be removed. Not that two channels were being (bridged), missing key word. Again our other TI launch pads do not bridge MCU pins to share booster pins via 0R. Hence surprise to find several under 5x magnification and later schematic. I have several EK-TM4C1294XL and x11 header has nearly all 128 pins from MCU + 4 booster pack headers.

The un-resolved question table 21-1 MCU pin 9 (A2/B6) and PinMux card J7 pin 64 (B6) shown in schematic as J7 pin 24 ADCINA2 does not have 0R bridge.

Had thought MCU pin 9 was not used so the schematic J7 pin 24 should read as ADCINB6. MCU pin 18 goes to PGA1 +IN so ADCINA2 can not be on J7 too? The point is ADC base address can be set for ADCA or ADCB to access MCU pin 9 marked as ADCINB6 on PinMux card and ADCINA2 in the schematic. Perhaps the booster header diagram in schematic could indicate both ADCINA2 and ADCINB6.

There was also an unintended bug CMPSS2 above snip PGA2 +IN bridged into P21(A3) via 0R, AG2 no longer owns this input as A3 is the new source Gx_ADCA3/P21. One really must pay attention to Fig.21-1 analog sub Mux comparators as AG1 now owns A3 for CMPSS1 via P21 shared with AG2.