Hi,
in TRM 3.2.2.3.3 Time-Base Counter Synchronization section.
The value of the phase register is loaded into the counter register when an input synchronization pulse
is detected (TBPHS → TBCTR). This operation occurs on the next valid time-base clock (TBCLK)
edge.
The delay from internal master module to slave modules is given by:
– if ( TBCLK = SYSCLKOUT): 2 x SYSCLKOUT
– if ( TBCLK != SYSCLKOUT):1 TBCLK
So if TBCLK=SYSCLKOUT, both EPWM1 and EPWM2 are UP-COUNT mode. if we sync EPWM1 clock with EPWM2 clock. And we set TBPHS=0.
The TBCLK of EPWM2 is still 2sysclkout delayed from TBCLK of EPWM1, right?
So if we want EPWM1 and EPWM2 TBCLK exactly the same, we should set EPWM2's TBPHS=TBPRD-2 to compensate the 2sysclkout delay, right?
