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CCS/TMS320F28388D: How to share RAM or variables between CPU and CM?

Andy Fung
Intellectual 875 points
Part Number: TMS320F28388D

Tool/software: Code Composer Studio

The section of GSx is shared by CPU1 and CPU2. If I assign a variable in GSx of CPU1 and change this value in CPU1, the value will be also updated in CPU2 in GSx. But I didn't see any share section between CPUx and CM in the F2828x block diagram. Does such a memory section exist? Or I have to use message ram CMTOCPU1MSGRAMx? If so, the total space of MSGRAMx is 4k, how can I share memory larger than that size?

  • 0
    TI__Guru** 113885 points

    Hi Andy,

    Message RAM is only RAM block which is available for this purpose. If need bigger RAM then you need to use this as ping-pong and move the data to local memory before over writing it.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Intellectual 875 points

    I tried to send message queue from CM to CPU1. The CM looks successfully send out the message queue. But the interrupt in CPU1 does not trigger. The following is the Pseudocode of both cores. Can you suggest what is missing? Thanks.

    In CM main():

    IPC_clearFlagLtoR(IPC_CM_L_CPU1_R, IPC_FLAG_ALL);

    IPC_initMessageQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_INT0, IPC_INT0);

    IPC_sync(IPC_CM_L_CPU1_R, IPC_FLAG31);

    IPC_sendMessageToQueue(IPC_CM_L_CPU1_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &TxMsg, IPC_BLOCKING_CALL);

    while(1);

    In CPU1 main():

    IPC_clearFlagLtoR(IPC_CPU1_L_CM_R, IPC_FLAG_ALL);

    IPC_initMessageQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_INT0, IPC_INT0);

    IPC_registerInterrupt(IPC_CPU1_L_CM_R, IPC_INT0, IPC_ISR1);

    IPC_sync(IPC_CPU1_L_CM_R, IPC_FLAG31);

    while(1);

    In CPU1,

    void IPC_ISR1()

    {

       IPC_readMessageFromQueue(IPC_CPU1_L_CM_R, &messageQueue, IPC_ADDR_CORRECTION_ENABLE, &RxMsg, IPC_NONBLOCKING_CALL);

       IPC_ackFlagRtoL(IPC_CPU1_L_CM_R, IPC_FLAG0);

    }

  • 0 in reply to Andy Fung
    Intellectual 875 points

    I ran both cores in debug mode. I set a break point inside IPC_ISR1() in CM. The flag PIEIFR.INTx9 is 0 in CPU1 after it goes into an infinite while loop. After the line IPC_sendMessageToQueue() is ran in CM, I went check the PIEIFR.INTx9 and found the flag is set. However, there is no stop on the break point inside ISR. Can you give any advice? Thanks.

  • 0 in reply to Andy Fung
    Intellectual 875 points

    Because I am asking a different question, I go ahead to open another new post for that and close this one.