tms320f28035 minimum clock frequency

Hi,

I need to reduce the clock frequency in order to reduce the power consumption, i need to keep CAN, SCI and ADC working under reduced

clock frequency.

at sprugl8b TMS320F2803x Piccolo System Control and and Interrupts Reference Guide (Rev. B) page 43 there is the note below:

The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is a
minimum of 50 MHz.

so i understand that the minimum clock  frequency at CPU can be  50MHZ / 4 = 12.5MHZ

is that conclusion right ? or the oscillator freq multiplied by  PLLCR[DIV] can be lower than 50MHZ?

thanks in advance

Ricardo -

When using the PLL yes, that is the minimum clock frequency.  If you bypass the PLL and use the input clock directly, you can have a CPU frequency of input clock/4 (which can be less than 50 Mhz).  Please also check the peripheral electrical specifications to determine if they themselves have frequency limitations for usage.