TMS320F28335: Biss C on Ti 28355 microcontroller

Hi.

F28335 doesnt support BiSS-C interface.
Newer devices, with Configurable Logic Block (CLB) F2837x etc., support BiSS_C interface.
Please refer to http://www.ti.com/tool/TIDM-1010 
Also, SPI or McBSP interface is not directly compatible with BiSS-C protocol.

Hi

There was some discussion on this thread that it can be done. Hence the question how to handle it if the data from the encoder is two words of 32 bits each.

http://e2e.ti.com/support/microcontrollers/c2000/f/171/p/317505/1104809?tisearch=e2e-sitesearch&keymatch=f28335%25252525252525252520biss%25252525252525252520c%25252525252525252520sensor#1104809

Hi,

As you can see in the above mentioned post, there is no example or application note, evaluation done for implementation using SPI.
As I mentioned earlier, protocol is not compliant to SPI as need for delay compensation exists in BiSS-C implementation.
Have you actually implemented the BiSS-C interface (based on recommendations from above post) using SPI? Are you using some external gates to implement this?

Hi

Yes we are implementing it using McBsp ( in SPI mode ). The HW has clk and receive data line. In SPI, we need to send slave select/frame sync  from DSP (F28335)  to the encoder. In the absence of FSX, how do we do this? We tried to use the example from TI loopback in McBsp and set up the FSXM=1 in PCR as mentioned in sprufb7a so that frame synchronisation is supplied by McBsp. But that didn't seem to work?  

Hi,

Before we go into the McBSP specific questions,
With the SPI mode, how do you plan to address the delay compensation needed by the BiSS-C protocol?
Are you planning to use this at very low frequency and short cable lengths?

Yes we are using it in 3/4Mbps and short cable length.

Hi,

Thanks for clarification. I believe now your question is really how to emulate control signals of McBSP in SPI mode.
I'll loop in McBSP expert for this.

Hi

Any update on how to do this?

Veena,

Sorry for the delay, I've been looking into this; there is likely some CPU overhead required here.  As you mentioned this is not supported natively.

I would send the 1st 32-bits only in that mode.  For the remaining 8 bits(40 bits total), then switch the McBSP size to 8 bits and initiate another transfer.  From what I understand the state of the clock/pins should be static after the 1st 32-bits so there would just be some added delay vs a native 40 bit transfer.

Best,

Matthew

Thanks for the response. My question was :

In an ideal scenario, the encoder would have a  Clk, data and frame sync signal.

However, we do not have the Frame Sync/Slave Enable signal.

So we looking into how we could emulate it to complete the interface operation. We tried to program the McBsp registers by setting up the FSXM=1 in PCR and FSGM in SRGR2 as mentioned in sprufb7a so that the internal frame generator could do it . But that didn’t seem to work. May be we misinterpreted it or didn’t implement it correctly?

I was wondering if there is any other option to do this?

Hi

Any thoughts on this?

Veena,

Looking into this I beleive you only need to enable FSXM in the PCR to allow the McBSP to supply the frame sync.  You will also need ot enable GRST(sample rate generator) and the FRST (frame sync logic). 

McbspaRegs.SPCR2.bit.GRST = 1;
McbspaRegs.SPCR2.bit.FRST = 1;
McbspaRegs.PCR.bit.FSXM = 1;

Best,
Matthew