It would seem SDK (FOC) state machine lacks any grace and is very rude to x49c hardware! There is no soft start (ramp_up) state machine rudely slams phase current entering EST_STATE_RS.
1. The problem is 2 fold as it requires excessive ADC channel input capacitance to counter measure instantaneous start period current spikes.
2. Low pass filter excess of 2200pF is simply a crude counter measure that leads to (transient) hang time in the crest of current wave peaks. We add (0) capacitance in our other HV systems since 1nF loading is expected from external differential amplifier. Any attempt to add low pass filer capacitance changes the precision of the current amplifier and invites transient hang time to the party.
That said why was there no ramp up wait time between EST_STATE_ROVERL and EST_STATE_RS? Might the crude methods of the few lead to the downfall of all at some point in this experiment?
Why is there no soft current startup between EST_STATE_CONSTSPEED and EST_STATE_RATEDFLUX_OL?
Can soft start (wait_time) be added begin EST_STATE_RS as to stop it from slamming CCMPS's DACS? Then a reasonable bypass filter value can be used rather than 2200pF. Also this missing wait time seems to cause major issues for the CMPSS DACA/B filters higher values being required to counter measure transient spikes that occur between state machine changes further into motor ID process.