Part Number: TMS320F28388D
I try to configure interrupt from the ECAT device - signal sync0. But it not work ( the interrupt function ISR_ECAT not called ).
I see in the ethercat memory that the register ECAT_SYNC0_TIME_START (0x990) is increment by 1e9 (every 1 second) as expected.
But bit 0 in the register status ESCSS_INTR_RIS is not set as expected ( only bit 2 is set due probably to AL register change, anyway write to register ESCSS_INTR_CLR not clear it )
Here is the relevant code , initDC_Intris called once after reset and ECAT configuration but IST_CAT never called
#define ECAT_MEMORY_EXT (Uint16*)0x00050000 // base address of ecat ram
#define ECAT_SYCLK_LATCH_ADDR (ECAT_MEMORY_EXT + 0x0918/BYTE_RES) // clock latch when write to 0x900
#define ECAT_SYCLK_OFFS_ADDR (ECAT_MEMORY_EXT + 0x0920/BYTE_RES) // clock offset, ststem clock = local clock + clock offset
#define ECAT_SYCLK_DIFF_ADDR (ECAT_MEMORY_EXT + 0x092c/BYTE_RES) // System Time Difference
#define ECAT_SYNC0_TIME_START (ECAT_MEMORY_EXT + 0x0990/BYTE_RES) //address of sunc0 period
#define ECAT_SYNC0_PERIOD (ECAT_MEMORY_EXT + 0x09A0/BYTE_RES) //address of sunc0 period
interrupt void ISR_ECAT (void)
{
ltest7++;
iHWREGH(ESC_SS_BASE + ESCSS_O_INTR_CLR) =1; // clear the intr
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge group 1 interrupt
EDIS;
}
void initDC_Intr ()
{
EALLOW; // Disable Hardware Protection of the registers, allow access
HWREGH(ESC_SS_BASE + ESCSS_O_INTR_CLR) =1; // clear previos intr
Uint32 tperiod =1000000000; // 1e9=>1second
HWREG32(ECAT_SYNC0_PERIOD)=tperiod;
Uint64 timenow= HWREG64(ECAT_SYCLK_ADDR);
Uint64 timestart = (timenow/tperiod +2 ) *tperiod;
HWREG64(ECAT_SYNC0_TIME_START)=timestart;
PieVectTable.ECATSYNC0_INT = ISR_ECAT; // set function pointer
HWREGH(ESC_SS_BASE + ESCSS_O_SYNC0_CONFIG)= (1 | ((uint16_t)((uint32_t)0xA5 << ESCSS_INTR_SET_WRITE_KEY_S) & ESCSS_INTR_SET_WRITE_KEY_M));
HWREGH(ESC_SS_BASE + ESCSS_O_INTR_MASK) |= (4 | ((uint16_t)((uint32_t)0xA5 << ESCSS_INTR_SET_WRITE_KEY_S) & ESCSS_INTR_SET_WRITE_KEY_M));
Interrupt_enable(INT_ECATSYNC0);
EDIS;
}
Avraham
