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TMS320F280049: EMI or bad ADC external circuit design issue

Sheldon He
Expert 8585 points
Part Number: TMS320F280049

Hi expert,

My customer is sampling HV with resistor divider and there is no amplifier as a buffer. They find the signal at ADC input pin gettting distorted when high power is on, we are not sure if this is related to F280049 or just caused by EMI. We have tried to cut the trace in PCB to disconnect resistor divider output to ADC input pin, in this circumstance waveform at divider output will not be distorted in high power conditions. 

We has external circuit design like below:

Below picture shows HV signal (green) and divided signal (yellow), the divided signal is connected to ADC input pin of F280049 

Could you give us some idea of how to identify the root cause? (maybe high signal source impedance or EMI?)

BTW, would like to know if 50ohm is a recommended internal resistance of signal source interfacing with F280049's ADC?

Thanks

Sheldon

  • 0
    TI__Guru 60865 points

    Hi Sheldon,

    The effective source impedance is 100+100+(6.8k || 402k) = 6.9k ohms

    If you use the equations in the TRM section "Choosing an Acquisition Window Duration" you'll find that this requires a S+H window of around 20ms to achieve 1/2 LSBs settling.  The maximum configuration for ACQPS of 511 gives 10ns * 512 = 5.1us at 100MHz, so that clearly isn't going to work.

    Alternately, if you assume a charge-sharing from the 100nF capacitor is the primary means of driving the input, then ln(100nF/12.5pF) > ln(4096/1), so the charge sharing provides at least settling to 1LSBs.  However, to keep the droop to within another 1LSBs of error, you need to settle from 2LSBs to 1LSBs in the time between samples, so you end up with a sample rate limitation of 

    dt = ln(2LSBs/1LSBs)*(6.9k*100nF) = ~500us, so you can only sample at about 2ksps before running into issues.