CCS/TMS320F28379D: c2000Ware incoherence in the exaple "cpu01_to_cpu02_ipcdrivers_lite" using the ram 0x0003FBF4 to pass a message from the CPU1 to CPU2

Tool/software: Code Composer Studio

Best Regards dear TI team

I have a question about the code in the example cpu01_to_cpu02_ipcdrivers_lite of the C2000Ware, exactry in the code of CPU1 cpu01_to_cpu02_ipcdrivers_lite_cpu01.c and is:

The code use the RAM direction 0x3FBF4 to pass a data from the CPU1 to CPU2  but in the documents:

1. TMS320F2837xD Dual-Core Microcontrollers Technical reference manual (SPRUHM8I) in the page 882 (Table 7-1. IPC Message RAM Read/Write Access) 

2.The TMS320F2837xD Architecture: Achieving a New Level of High Performance (SPRT720) in the page 4 (Figure 2. Simplified Memory Map)

You can see that the RAM direction 0x3FBF4 is used to pass only messages from the CPU2 to CPU1 but no for the purpose of the code (send a message from the CPU1 to CPU2)

I Attached part of the code(only until use the funtion to send the message) of the example cpu01_to_cpu02_ipcdrivers_lite_cpu01.c and the parts where the address is defined is highlight

1.  #define CPU02_TO_CPU01_PASSMSG 0x0003FBF4      // CPU02 TO CPU01 MSG RAM  (inclusive in the coments say that is for pass message from CPU2 to CPU1)

2. uint32_t *pulMsgRam;

3. pulMsgRam = (void *)CPU02_TO_CPU01_PASSMSG;

4. IPCLiteLtoRDataWrite(IPC_FLAG0, pulMsgRam[0],(uint32_t)usWWord16, IPC_LENGTH_16_BITS, IPC_FLAG31);

I don't have idea what happen, maybe I don't undestand the mapping of the RAM of the code in the example have a mistake, please help me to understand this doubt.

Thanks

//###########################################################################
//
//
// FILE:   cpu01_to_cpu02_ipcdrivers_lite_cpu01.c
//
// TITLE:  CPU01 to CPU02 IPC Drivers (CPU01) Example
//
//! \addtogroup dual_example_list
//! <h1> CPU01 to CPU02 IPC Lite Drivers (cpu01_to_cpu2_ipcdrivers_lite)</h1>
//!
//! This example application demonstrates the use of the CPU01 to CPU02
//! IPC Lite Driver Functions which allow the CPU01 to read/write to
//! addresses on the CPU02. CPU02 to CPU01  MSG RAM is used to pass the
//! addresses of local variables between the processors.
//!
//! \b Watch \b Variables on CPU01: \n
//!   - ErrorCount - Counts # of errors
//!   - usWWord16  - 16-bit word to write to CPU02
//!   - ulWWord32  - 32-bit word to write to CPU02
//!   - usRWord16  - 16-bit word to read from CPU02
//!   - ulRWord32  - 32-bit word to read from CPU02
//!
//! \b Watch \b Variables on CPU02: \n
//!  - ErrorFlag - Indicates an unrecognized command was sent from CPU01
//!                to CPU02.
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v3.08.00.00 $
// $Release Date: Mon Dec 23 17:32:30 IST 2019 $
// $Copyright:
// Copyright (C) 2013-2019 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without 
// modification, are permitted provided that the following conditions 
// are met:
// 
//   Redistributions of source code must retain the above copyright 
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the 
//   documentation and/or other materials provided with the   
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_Ipc_drivers.h"

//
// Defines
//
#define CPU02_TO_CPU01_PASSMSG   0x0003FBF4    // CPU02 TO CPU01 MSG RAM
                                               // offsets for passing addresses
#define SETMASK_16BIT            0xFF00        // Mask for setting bits of
                                               // 16-bit word
#define CLEARMASK_16BIT          0xA5A5        // Mask for clearing bits of
                                               // 16-bit word
#define SETMASK_32BIT            0xFFFF0000    // Mask for setting bits of
                                               // 32-bit word
#define CLEARMASK_32BIT          0xA5A5A5A5    // Mask for clearing bits of
                                               // 32-bit word

//
// Globals
//
uint16_t ErrorFlag;

//
// Main
//
void
main(void)
{
    uint16_t ErrorCount = 0;
    uint16_t usWWord16;
    uint32_t ulWWord32;
    uint16_t usRWord16;
    uint32_t ulRWord32;
    uint32_t *pulMsgRam;

//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();

//
// Step 2. Initialize GPIO:
//
// InitGpio();  // Skipped for this example

//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
    DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

#ifdef _STANDALONE
#ifdef _FLASH
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH);
#else
    //
    //  Send boot command to allow the CPU02 application to begin execution
    //
    IPCBootCPU2(C1C2_BROM_BOOTMODE_BOOT_FROM_RAM);
#endif
#endif

//
// Initialize all variables used in example.
//
    ErrorFlag = 0;
    usWWord16 = 0x1234;
    ulWWord32 = 0xABCD5678;
    usRWord16 = 0;
    ulRWord32 = 0;
    pulMsgRam = (void *)CPU02_TO_CPU01_PASSMSG;

//
// Spin here until CPU02 is ready
//
    while(!IPCRtoLFlagBusy(IPC_FLAG17));
    IPCRtoLFlagAcknowledge(IPC_FLAG17);

//
// 16 and 32-bit Data Writes
// Write 16-bit word to CPU02 16-bit write word variable.
//
    IPCLiteLtoRDataWrite(IPC_FLAG0, pulMsgRam[0],(uint32_t)usWWord16,
                         IPC_LENGTH_16_BITS,
                         IPC_FLAG31);