Hi Vivek,

I found that we can select the ADCA-ADCD, But just for understanding is it possible to share few channels of ADCA to CPU1 and few channels to CPU2. Seems it look like not possible but for clarification if you can confirm will help me to save my time.

Hi Vivek.

Thanks for update. 

Your last line " Please note result register are accessible from both the CPU always." Do you mean both the CPUs can access the ADC register simultaneously ?

Hi Vivek,

I am facing issue with ADCC and ADCD in CPU2. I have tested these both ADCs in CPU1 and it was working perfectly. Now I have transfer these two ADCs to CPU2 by transferring the ownership to CPU2.

In CPU1 I have did the below configuration

DevCfgRegs.CPUSEL11.bit.ADC_C = 1; // ADC C ownership to CPU2
DevCfgRegs.CPUSEL11.bit.ADC_D = 1; // ADC D ownership to CPU2
CpuSysRegs.PCLKCR13.bit.ADC_C = 1; // ADC C Clock enable
CpuSysRegs.PCLKCR13.bit.ADC_D = 1; // ADC D Clock enable

Code is stop working in below function

void readADCC()
{
AdccRegs.ADCSOCFRC1.all = 0x003F; //SOC2-SOC5

while(AdccRegs.ADCINTFLG.bit.ADCINT1 == 0);
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;

adcChannelData[0] = AdccResultRegs.ADCRESULT2;
adcChannelData[1] = AdccResultRegs.ADCRESULT3;
adcChannelData[2] = AdccResultRegs.ADCRESULT4;
adcChannelData[3] = AdccResultRegs.ADCRESULT5;
}

Please let me know if anything is required to configure for CPU2.

Hi Vivek,

Code stuck on the below line of ADCC interrupt check

   while(AdccRegs.ADCINTFLG.bit.ADCINT1 == 0);

Please suggest which thing I need to check in the configuration.

Same case is happen with ADCD as well. Due to interrupt it is not executing next step. Interrupt is not getting generated for both ADCC and ADCD in CPU2.

Please suggest the correct area where this is an issue. 

Code stuck on the below line of ADCD interrupt check

   while(AdcdRegs.ADCINTFLG.bit.ADCINT1 == 0);

Hi Viviek,

I have checked in the debug and found that the below mentioned interrupt registers are not set initialize.

AdccRegs.ADCINTSEL1N2.bit.INT1SEL = 1; //end of SOC5 will set INT1 flag
AdccRegs.ADCINTSEL1N2.bit.INT1E = 1; //enable INT1 flag
AdccRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //make sure INT1 flag is cleared

I have already called in the init function but it is not set in the CPU2 code. Same is working with CUP1. Something is missing.

Please can check what exactly I missed in the configuration  in CPU1 or CPU2. If possible share as soon as possible. I am stuck in the ADC.

Meanwhile I am also try to resolve the issue.

Hi Vivek,

As per your suggestion I have raise new ticket. Please reply on that post.

Actually Clock is enable, Ownership is transfer to CPU2 only ADCC and ADCD interrupt is not getting enable. We will discuss in the new post.

refer new Post title.

"CCS/TMS320F28379D: ADCC & ADCD is not working in CPU2"