TMS320F28379D: TI Design Drive with SDFM peripheral

Chai,

Did you look into C2000Ware SDFM examples?

Regards,

Manoj

Hi Manoj

I have looked at the SDFM examples in C2000Ware. My question was more related to the timing of the start and end of conversion. With a 20MHz clock on the AMC1306x, sinc3 filter and OSR of 64, the sampling period lasts for 9.6us. This means that if the width of the PWM high pulse or low pulse for one of the phases is shorter than that, I cannot use that phase to measure current without coupling in a lot of noise into the system. How do I use the Fast Current Loop Library with an SDFM peripheral in that case?

This is my understanding of how the sampling should work - Since my switching frequency is 75kHz, the shortest period I can have is at 50% duty cycle when both high and low pulses = 6.7us. This means that I'd have to know the duty cycle of each phase every cycle, compute the high pulse and low pulse duration and only measure the currents when those pulses are longer than 9.6us. I'd also have to center the sampling period in the middle of the pulse by starting the ADC 4.8us before the center of the pulse and reading it 4.8us after. Do I have to do all of this? The documentation for the FCL library seems to say that we simply pass a handler to the ADC device. Does that mean that the FCL library needs to be told what kind of ADC it is connected to, and then has different timing behavior based on that?

On a slightly different note, what is the acceptable delay for the ADC? My switching frequency is 75kHz. I read some sources that said that using a sinc filter for the SDFM that has its first notch on the switching frequency will give the best results as it will completely eliminate switching noise from the measurement. However, this introduces a delay equal to 3x the switching period in the case of the sinc3 filter. It seems like a better idea to use a much lower OSR and time the start and end of conversion so it never sees the switching noise. This will reduce the group delay of the signal chain by having a shorter sampling window and by allowing the use of a higher frequency analog low pass filter on the input of the modulator. Isn't this a preferable solution?

Thanks
Chai

Chai,

I shall forward your question to one of our system engineers. Please expect an response in within 2 business days.

Regards,

Manoj

Your basic understanding of sampling is right, the DesignDrive example takes care of positioning the sampling window based on centering the timing on either side of the effective sampling instance (midpoint of ON or OFF time). If you have 192 samples making a sync3 filter, then the SDFM is started 96 SDFM clocks ahead of the preferred sampling instance and will accumulate / end until 96 SDFM clocks from the same preferred instance.

However, in our example, SDFM is used to measure the shunt voltage that is in series with the phase for direct phase current measurement and is therefore the effect of PWM is moderated by load inductance. The dutycycle of inverter half bridge does not matter.

The library is meant to be generic and cannot be tied to any specific peripheral and that is the reason for the handler.

You asked about acceptable delay of ADC, well, ADC sampling rate is fixed by the clock frequency and associated prescaler. Wondering if you meant SDFM. Again, you have a choice of OSR and sync3 to fiddle around and experiment. My approach would be that 'as long as I get the current feedback within a time delay that lets me do the entire FOC loop  without losing out pwm update' I would be fine. Dont know how else to respond to that query. 

Hi Ramesh

I am using a shunt resistor in series with the phase so I understand the point that the PWM edges' effects are moderated by the load inductance.

However, I have 2 follow up questions -

You say the duty cycle does not matter, does that mean that the sampling window is such that it samples over a full PWM cycle regardless of duty cycle? Does that mean that the modulator clock and OSR need to be set such that - 
- The sampling period is nearly a full PWM cycle? (1/75e3 = ~13us = OSR/CLK => OSR=256; CLK=20MHz)
OR
- The measurement settling time is nearly a full PWM cycle? (13us = FiltOrder*OSR/CLK => sinc3 filtOrder = 3; OSR=72; CLK=20MHz)

Also, I don't see where in the example the SDFM peripheral is started ahead of time. In the motorControlISR function, the getSDFMCurrent function is called at which point current is measured. How is the timing so that the ISR is triggered 64 cycles ahead of the middle of the measuring period specified? (64 because in the example the OSR is chosen as 128)

I don't entirely understand the last point about choosing the OSR and sinc3. How much time delay is acceptable so that I didn't lose a PWM update? For a 75kHz PWM frequency and 1us of processing time on the F28379D, I would need my ADC sampling time to be under 13.3-1=12.3us? How would I trigger the sampling at the end of the previous PWM update? Could I alternatively run my control loop at a much lower frequency like 25kHz and sample over multiple PWM cycles and have my filter notch at 75KHz to reduce noise in my measurement? My motor fundamental frequency is only 1.6kHz so I could run my control loop quite slow. 

Sorry for so many questions. I'm just trying to figure out how to use the library 
Regards
Chai

You can choose to set one full pwm cycle, your choice, but it does not have to be. Wider the window, lower the noise floor and so you make the tradeoff.

SDFM is reset by EPWM11 CMPC I think. Once it is set up this way, the EPWM peripheral provides the periodic reset. Review the initialization section of the code. 

I recommend you to spend some time digging into the code to figure out more details.

The thread has been silent for 10 days, so let us know if your query is resolved or you may close the thread. Thanks.