Compiler/LAUNCHXL-F28379D: EABI migration booting from flash after reset

Benjamin,

Do the map files look similar for COFF and EABI?  Any missing routines?

From the EABI migration guide, please review the section for "Conditional Linking" since COFF and EABI behavior are essentially opposite:

     https://software-dl.ti.com/ccs/esd/documents/C2000_c28x_migration_from_coff_to_eabi.html

Potentially you are not retaining enough functions or sections.  You may need more than one .retain directive added to your assembly file(s).

And if some COFF symbols are involved in the assembly then you will also need to handle the leading underscore which only applies to COFF.   Also mentioned in above guide.

Also, if you could provide details on how to reproduce the issue then it would be easier to help.

Thanks
Greg

I looked at the two map files, I noticed this difference:

EABI:

.reset 0 003fffc0 00000000 DSECTEABI:

COFF:

.reset 0 003fffc0 00000002 DSECT

003fffc0 00000002 rts2800_fpu32.lib : boot28.asm.obj (.reset)

Also noticed the symbols with  __TI_*** still had the double underscore eg. __TI_Handler_Table_Limit , not sure if this would cause any issues.

Benjamin,

I did similar testing with the c2000ware blink project and obtained similar linker map results as you showed.

However, both executables disassembled with expected code_start entry points and both worked in CCS to "restart":

COFF:

TEXT Section codestart (Little Endian), 0x2 words at 0x00000000

00000000        code_start:

00000000   0040   LB           0x008523

00000001   8523

…

00008523        _c_int00:

00008523   28ad   MOV          SP, #0x0400

EABI:

TEXT Section codestart (Little Endian), 0x2 words at 0x00000000

00000000        code_start:

00000000   0040   LB           0x008668

00000001   8668

…

00008668        _c_int00:

00008668   28ad   MOV          SP, #0x0400

However, when testing for "CPU reset" both EABI and COFF failed with:

   Break at address "0x3ff16a" with no debug info available, or outside of program code.

My limited understanding about "CPU resets" is that is requires boot mode pins to be set correctly which clearly are not set in my test projects.

If your COFF build works and your EABI build does not, then perhaps the boot mode pins are being set in an assembly routine that needs to have .retain added to it's section definition?

Regards,

Greg

In addition to above question (if resets work with your COFF builds), could you please also provide your linker cmd file and map files?  For both COFF and EABI? 

thanks

Greg

Thanks for the reply, I'll take a look at the boot pins once I get a chance. In the meantime here's my cmd file, just using directives on the same file for both COFF and EABI.

MEMORY
{
PAGE 0 :  /* Program Memory */
          /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */
          /* BEGIN is used for the "boot to Flash" bootloader mode   */

   BEGIN           	: origin = 0x080000, length = 0x000004
   RAMM0           	: origin = 0x000122, length = 0x0002DE
   RAMD0           	: origin = 0x00B000, length = 0x000800


   RAMLS4	   : origin = 0x00A000, length = 0x000800
   RAMLS5	   : origin = 0x00A800, length = 0x000800

   RESET           	: origin = 0x3FFFC0, length = 0x000002

   /* Flash sectors */
   FLASHA           : origin = 0x080004, length = 0x001FFC	/* on-chip Flash */
   FLASHB           : origin = 0x082000, length = 0x002000	/* on-chip Flash */
   FLASHC           : origin = 0x084000, length = 0x002000	/* on-chip Flash */
   FLASHD           : origin = 0x086000, length = 0x002000	/* on-chip Flash */
   FLASHE           : origin = 0x088000, length = 0x008000	/* on-chip Flash */
   FLASHF           : origin = 0x090000, length = 0x008000	/* on-chip Flash */
   FLASHG           : origin = 0x098000, length = 0x008000	/* on-chip Flash */
   FLASHH           : origin = 0x0A0000, length = 0x008000	/* on-chip Flash */
   FLASHI           : origin = 0x0A8000, length = 0x008000	/* on-chip Flash */
   FLASHJ           : origin = 0x0B0000, length = 0x008000	/* on-chip Flash */
   FLASHK           : origin = 0x0B8000, length = 0x002000	/* on-chip Flash */
   FLASHL           : origin = 0x0BA000, length = 0x002000	/* on-chip Flash */
   FLASHM           : origin = 0x0BC000, length = 0x002000	/* on-chip Flash */
   FLASHN           : origin = 0x0BE000, length = 0x002000	/* on-chip Flash */

PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */

   BOOT_RSVD       : origin = 0x000002, length = 0x000120     /* Part of M0, BOOT rom will use this for stack */
   RAMM1           : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAMD1           : origin = 0x00B800, length = 0x000800

   RAMLS0      : origin = 0x008000, length = 0x000800
   RAMLS1      : origin = 0x008800, length = 0x000800
   RAMLS2	   : origin = 0x009000, length = 0x000800
   RAMLS3	   : origin = 0x009800, length = 0x000800


   RAMGS0     : origin = 0x00C000, length = 0x002000
   RAMGS1     : origin = 0x00E000, length = 0x002000
   RAMGS2     : origin = 0x010000, length = 0x004000
   RAMGS3     : origin = 0x014000, length = 0x004000
   RAMGS4     : origin = 0x018000, length = 0x004000     /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */

   CPU2TOCPU1RAM   : origin = 0x03F800, length = 0x000400
   CPU1TOCPU2RAM   : origin = 0x03FC00, length = 0x000400

   CLA1toCPU1MSGRAM		: origin = 0x00001480, length = 0x80
   CPU1toCLA1MSGRAM		: origin = 0x00001500, length = 0x80
}

SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASHF      PAGE = 0, ALIGN(4)
   .text               : >> FLASHB | FLASHC | FLASHD | FLASHE      PAGE = 0, ALIGN(4)
   codestart           : > BEGIN       PAGE = 0, ALIGN(4)
   /* Allocate uninitalized data sections: */
   .stack              : > RAMM1       PAGE = 1
   .switch             : > FLASHB      PAGE = 0, ALIGN(4)
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT /* not used, */

	RFFTadcVdata    : > RAMGS0,	   PAGE = 1
	RFFTadcIdata    : > RAMGS1,	   PAGE = 1
	RFFTindata      : > RAMGS2,	   PAGE = 1
	RFFToutdata     : > RAMGS3,	   PAGE = 1
	RFFTcoefdata    : > RAMGS4,	   PAGE = 1
	Perturbation	: >> FLASHG | FLASHH,	   PAGE = 0
	CPU12CPU2		: > CPU1TOCPU2RAM, PAGE = 1


  Cla1Prog        : LOAD = FLASHD,
                  RUN = RAMLS5,
                  LOAD_START(_Cla1funcsLoadStart),
                  LOAD_END(_Cla1funcsLoadEnd),
                  RUN_START(_Cla1funcsRunStart),
                  LOAD_SIZE(_Cla1funcsLoadSize),
                  PAGE = 0, ALIGN(4)

  .const_cla      :  LOAD = FLASHD,
                   RUN = RAMLS4,
                   RUN_START(_Cla1ConstRunStart),
                   LOAD_START(_Cla1ConstLoadStart),
                   LOAD_SIZE(_Cla1ConstLoadSize),
                   PAGE = 0

  .bss_cla        : > RAMLS4, PAGE = 0
  .scratchpad     : > RAMLS4, PAGE = 0

   /* CPU1 CLA1 Comunication */
   CPU1toCLA1 		: > CPU1toCLA1MSGRAM,	PAGE = 1
   CLA1toCPU1		: > CLA1toCPU1MSGRAM,	PAGE = 1
   FPUmathTables	   : > FLASHF,        PAGE = 0
   /* Initalized sections go in Flash */


#if defined(__TI_EABI__)
   .init_array         : > FLASHC,       PAGE = 0,       ALIGN(4)
   .bss                : > RAMD1,       PAGE = 1
   .bss:output         : > RAMD0,       PAGE = 0
   .bss:cio            : > RAMD1,       PAGE = 1
   .data               : > RAMD1,       PAGE = 1
   .sysmem             : > RAMD1,       PAGE = 1
   /* Initalized sections go in Flash */
   .const              : > FLASHF,       PAGE = 0,       ALIGN(4)
#else
   .pinit              : > FLASHB,       PAGE = 0,       ALIGN(4)
   .ebss               : > RAMD1    	 PAGE = 1
   .esysmem            : > RAMD1,       PAGE = 1
   .cio                : > RAMD1,       PAGE = 1
	.econst             : >> FLASHF | FLASHG | FLASHH      PAGE = 0, ALIGN(4)

#endif


#ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        #if defined(__TI_EABI__)
            .TI.ramfunc : {} LOAD = FLASHD,
                                 RUN = RAMD0,
                                 LOAD_START(RamfuncsLoadStart),
                                 LOAD_SIZE(RamfuncsLoadSize),
                                 LOAD_END(RamfuncsLoadEnd),
                                 RUN_START(RamfuncsRunStart),
                                 RUN_SIZE(RamfuncsRunSize),
                                 RUN_END(RamfuncsRunEnd),
                                 PAGE = 0, ALIGN(4)
        #else
            .TI.ramfunc : {} LOAD = FLASHD,
                             RUN = RAMD0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             LOAD_END(_RamfuncsLoadEnd),
                             RUN_START(_RamfuncsRunStart),
                             RUN_SIZE(_RamfuncsRunSize),
                             RUN_END(_RamfuncsRunEnd),
                             PAGE = 0, ALIGN(4)
        #endif
    #else
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAMD0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_SIZE(_RamfuncsLoadSize),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
                         RUN_SIZE(_RamfuncsRunSize),
                         RUN_END(_RamfuncsRunEnd),
                         PAGE = 0, ALIGN(4)
    #endif

#endif


   /* The following section definitions are required when using the IPC API Drivers */
    GROUP : > CPU1TOCPU2RAM, PAGE = 1
    {
        PUTBUFFER
        PUTWRITEIDX
        GETREADIDX
    }

    GROUP : > CPU2TOCPU1RAM, PAGE = 1
    {
        GETBUFFER :    TYPE = DSECT
        GETWRITEIDX :  TYPE = DSECT
        PUTREADIDX :   TYPE = DSECT
    }

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Benjamin,

Please also provide the linker map files for both COFF and EABI.

Thanks
Greg