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TMS320F28027: Interrupt delay for GPIO or capture

Emma Wang
Expert 4820 points
Part Number: TMS320F28027

Hi expert,

my customer wants to use comparator output to GPIO or capture to achieve edge interrupt on F28027.

However, they found the latency is too large, about 700ns.

so, my questions are:

1. where can i get the interrupt latency, the time from GPIO input toggle and CPU service the interrupt.

(I think it should be several CPU clycles, however I can not find it now.)

2.if there is another method to achieve edge interrupt for comparator module?

BR

Emma

  • 0
    TI__Genius 17315 points

    Emma,

    A latency of 700 ns might look high, but for a device operating between 40 MHz (25 ns) to 60 MHz (16.67 ns) this translates between 28 and 42 cycles.  The minimum latency for an interrupt (to when the processing of the ISR occurs) is 14 cycles for internal interrupts and 16 cycles for external interrupts.  The F2802x data sheet show the GPIO timing could be another few cycle or more depending upon GPIO input qualification (see SPRS523 GPIO - Input Timing on page 116).  Perhaps have your customer double-check their input qualification settings.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • 0 in reply to Ken Schachter
    TI__Expert 4820 points

    Ken，

    Ken Schachter said:
    for a device operating between 40 MHz (25 ns) to 60 MHz (16.67 ns) this translates between 28 and 42 cycles.

    what does this mean？ I did not fully understand.

    By the way, how do you get the conclusion.

    Ken Schachter said:
    The minimum latency for an interrupt (to when the processing of the ISR occurs) is 14 cycles for internal interrupts and 16 cycles for external interrupts. 

    I find in the datasheet, and see these content. how to understand these parameters.

    BR

    Emma

  • 0 in reply to Emma Wang
    TI__Genius 17315 points

    Emma,

    You told me that the customer is using the F28027, but did not tell me which device operating speed/frequency they are using.  So I used a range of slowest to fastest by simply dividing the 700 ns by the instruction cycle time for each device operating speed/frequency to determine the number of cycles.  Does this make sense now?

    For minimum latency for an interrupt please see the slide (from the workshops) below:

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken