CCS/TMS320F280049: SDFM: PWM sync problem

Tool/software: Code Composer Studio

I am using SDFM module in TMS320F280049 with AMC1035. 

I would like to have synchronized measurement with PWM1 module which generates signal at 50kHz .

My problem is when I enable synchronization from PWM1 and a particular interrupt from SDFM occurs I get a wrong results. The interrupt is invoked in periodic way of 20us which is as expected. When I disable PWM synchronization I can get a correct result in ISR. The PWM1 is configured to generate SOC_A when time-base counter is equal to period. So it should be 

My configuration is following:
SDFM1 Filter Settings : Only FILTER4 is enabled, SINC3, OSR 128, SD_CLK = 10MHz, @ data rate frequency = 78kHz, latency 38.4us

Initialization code: It is based on example code from C2000 ware. 

void init_SDFM(void)
{
    //pin config
    GPIO_setDirectionMode(58, GPIO_DIR_MODE_IN);
    GPIO_setMasterCore(58, GPIO_CORE_CPU1);
    GPIO_setPadConfig(58, GPIO_PIN_TYPE_STD);
    GPIO_setQualificationMode(58, GPIO_QUAL_ASYNC);
    GPIO_setPinConfig(GPIO_58_SD_D4);

    GPIO_setDirectionMode(59, GPIO_DIR_MODE_IN);
    GPIO_setMasterCore(59, GPIO_CORE_CPU1);
    GPIO_setPadConfig(59, GPIO_PIN_TYPE_STD);
    GPIO_setQualificationMode(59, GPIO_QUAL_ASYNC);
    GPIO_setPinConfig(GPIO_59_SD_C4);

    //
    // Configure Input Control Unit: Modulator Clock rate = Modulator data rate
    //
    SDFM_setupModulatorClock(SDFM1_BASE, SDFM_FILTER_4, SDFM_MODULATOR_CLK_OFF);
    SDFM_configDataFilter(SDFM1_BASE, (SDFM_FILTER_4 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(128)), (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE | SDFM_SHIFT_VALUE(0x0006)));
    //
    // Enable Master filter bit: Unless this bit is set none of the filter
    // modules can be enabled. All the filter modules are synchronized when
    // master filter bit is enabled after individual filter modules are enabled.
    //
    SDFM_enableMasterFilter(SDFM1_BASE);

    //
    // Set the output data format
    //
    SDFM_setOutputDataFormat(SDFM1_BASE, SDFM_FILTER_4, SDFM_DATA_FORMAT_16_BIT);

    //
    // Disable PWM sync 
    //
    //SDFM_disableExternalReset(SDFM1_BASE, SDFM_FILTER_4);

    //
    // PWM signals can synchronize SDFM1 filters. Enabling PWM sync for SDFM
    // filters.
    //
    SDFM_enableExternalReset(SDFM1_BASE, SDFM_FILTER_4);
    SDFM_setPWMSyncSource(SDFM1_BASE, SDFM_FILTER_4, SDFM_SYNC_PWM1_SOCA);

    //
    // Enable interrupts
    //
    // Following SDFM interrupts can be enabled / disabled using this function.
    // Enable  modulator clock failure
    // Enable  data filter acknowledge
    //

    SDFM_enableInterrupt(SDFM1_BASE, SDFM_FILTER_4, (SDFM_MODULATOR_FAILURE_INTERRUPT | SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));

/*
    SDFM_disableInterrupt(SDFM1_BASE, SDFM_FILTER_4,
            (SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT |
             SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT));
*/
    //
    // Enable master interrupt so that any of the filter interrupts can trigger
    // by SDFM interrupt to CPU
    //
    SDFM_enableMasterInterrupt(SDFM1_BASE);
}

Thank you.