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TMS320F28035: I2C Minimal Fall Time

Nicolás Román
Intellectual 960 points
Part Number: TMS320F28035


Dear C2000 team, 

Can you help me with some clarifications?

Overview:
The datasheet for theTMS320F28035 quote a minimal fall time of tf(SDA) = 11.4ns for the I2C interface. The EEPROM with which it should communicate with has a minimal fall time of below 10ns. on the prototype both devices are communicating with each other. While reviewing the project the mismatch of 2-3ns was discovered.

Question:
Can you help me understand if there is a technical reason for the 11.4ns and if it is safe to leave the design as it is, or if a RC is required to "slow down" the fall time?

I am looking forward for your feedback.

Best regards,
Nico

  • 0
    TI__Mastermind 45526 points

    Hi Nico,

    What I2C clock frequency are you planning to use? I'd suggest looking at the NXP I2C spec and make sure your eeprom meets the standard or fast modes based on the SCL clock speed you plan to use.

    I believe the 11.4 ns is specific to the F2803x, i.e. how fast it can pull the line low.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    TI__Intellectual 960 points

    Hi Kevin,

    Thank you for the feedback.

    • The I2C bus should be in the "fast mode" -> 400kHz
    • can you help me understand what the side note of "imputes tolerance" in the DS for tf(SDA) is referring to? 
    • measurements showed a fall time of 2.2ns for the F28035, while the EEPROM was much slower with 10ns 
    • according the NXP specification the fall time should be 20*(Vdd/5.5V) ns for the fast mode -> since 3.3V are used it would result in a 12ns fall time. Does it mean that the line needs to be slowed down with an RC to have a proper "fast mode communication"?

    Best regards,
    Nico 

  • 0 in reply to Nicolás Román
    TI__Mastermind 45526 points

    Hi Nico,

    Can you provide waveforms showing SCL clock speed and 2.2ns fall time witnessed? Note that standard mode does not have a fall time MIN spec, so if it's working within the standard mode speed (<= 100 KHz) then this shouldn't be a concern.

    Nicolás Román said:
    can you help me understand what the side note of "input tolerance" in the DS for tf(SDA) is referring to? 

    I believe this is referring to the input filtering included on the SCL and SDA lines for spike supression.

    Nicolás Román said:
    according the NXP specification the fall time should be 20*(Vdd/5.5V) ns for the fast mode -> since 3.3V are used it would result in a 12ns fall time. Does it mean that the line needs to be slowed down with an RC to have a proper "fast mode communication"?

    I don't think adding a RC filter for this purpose should be necessary when operating in Fast mode.

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Prodigy 60 points

    Hi Kevin

    Thank you for your feedback.

    See attached pictures for measured fall times. The upper part shows SCL and SDA with 10us/div. The lower part shows the zoomed in falling edge of SDA line (5ns/div). Picture 1 zooms in when MCU is sending. Picture 2 zooms in when EEPROM is sending. (Please ignore the "Measure" section. These values are not related to the zoomed signal)

    I'll discuss with my team if we can live with standard mode or if we accept that the design is infringing I2C specification in fast mode. (Although I still don't understand the technical reason why fall time is limited in fast mode while standard mode accepts signals without limitations.)

    Best regards,
    Adrian

  • 0 in reply to Ad
    TI__Mastermind 45526 points

    Hi Adiran,

    Thanks for sharing the waveforms. I can tell it is indeed working in Fast mode (~400 KHz).

    What I2C eeprom are you planning on using, if you don't mind sharing? Maybe its datasheet doesn't have a MIN requirement listed.

    user3829587 said:
    I'll discuss with my team if we can live with standard mode or if we accept that the design is infringing I2C specification in fast mode. (Although I still don't understand the technical reason why fall time is limited in fast mode while standard mode accepts signals without limitations.)

    I find this difference between the standard & fast mode spec strange as well, I'm not certain of the reason. I found the below E2E thread that states it's for EMI reasons and not a hard requirement.

    https://e2e.ti.com/support/interface/f/138/t/723840?TCA9539-I2C-input-rise-and-fall-time-for-FAST-MODE

    Best,

    Kevin

  • 0 in reply to Kevin Allen18
    Prodigy 60 points

    Hi Kevin

    Thank you again for your feedback and the link!

    EEPROM is a Microchip 24LC16B-E/SN. So you are right, fall time is not a problem for this EEPROM. It's only a "problem" for general I2C- and TI TMS320F28035 specification.

    Best regards,
    Adrian

  • 0 in reply to Ad
    TI__Mastermind 45526 points

    Hi Adrian,

    OK, you should be fine then. The 24LC16B-E/SN doesn't have a MIN T_F spec and it's T_OF (output fall time) is within the I2C and F2803x spec.

    Let me know if there's anything else I can help with.

    Best,

    Kevin