Hi,
I am using a TMS320F28032 for a multi stage Flyback design.
So far everything is working as purposed.
Controller is clocked by a 20Mhz XTAL. SYSCLOCK is (measured with GPIO18) 60MHz and LSPCLK ist 15MHz.
I already set up 3 phase shifted PWMs with 100 kHz each (Period register is 600 in Count-Up mode). I see on my scope that those PWMs work as purposed (100kHz each and 120° phase shift each)
ePWM1 generates a SOC Pulse as soon as its counter is zero. This riggers my high priority SOCs 0 ... 2 to sample ADCIN0A,ADCIN0B and ADCIN1A
SOC2 is configured to throw an interrupt. (the only one so far on my controller!)
EALLOW; AdcRegs.ADCCTL1.bit.INTPULSEPOS = 0; // INT pulse generation occurs when ADC begins conversion -> early interrupt AdcRegs.INTSEL1N2.bit.INT1E = 1; // Enable ADCINT1 AdcRegs.INTSEL1N2.bit.INT1CONT = 1; // continuous sampling for ADCINT1 AdcRegs.INTSEL1N2.bit.INT1SEL = 0x02; // End of conversion of SOC2 will trigger ADCINT1 AdcRegs.INTSEL1N2.bit.INT2E = 1; // Enable ADCINT2 AdcRegs.INTSEL1N2.bit.INT2CONT = 1; // continuous sampling for ADCINT2 AdcRegs.INTSEL1N2.bit.INT2SEL = 0x07; // End of conversion of SOC7 will trigger ADCINT2 AdcRegs.SOCPRICTL.bit.SOCPRIORITY = 0x03; // SOC0-SOC2 are high priority, SOC3-SOC15 are in round robin mode EDIS;
The interrupt is periodically thrown in the right mannor right after SOC2_EOC. But is see already with some stupid data shifts or even only while acknowledging the Interrupt servicing takes rediculous long times.
typedef struct ADC_Sampledata ADC_Sampledata;
/*******************************************************************************
* UNION : ADC_Data
* DESCRIPTION :
* Allows a int to be written directly in to a _iq variable.
*******************************************************************************/
union Sample_ARG
{
_iq15 m_IQ15;
unsigned int m_Int;
};
/*******************************************************************************
* STRUCT : ADC_Sampledata
* DESCRIPTION :
* contains the high speed sampled adc values
*******************************************************************************/
struct ADC_Sampledata
{
Sample_ARG AC_Input;
Sample_ARG Rail_Feedback;
Sample_ARG VIN_RECT;
};
/* align sample data array */
#pragma DATA_ALIGN ( Sampledata , 8 );
ADC_Sampledata Sampledata;
// ISR called at end of conversion of high priority fast ADCs
__interrupt void ADC1_EOC(void)
{
GpioDataRegs.GPASET.bit.GPIO10 = 1; // on + off takes 260ns
Sampledata.AC_Input.m_Int =(AdcResult.ADCRESULT0)<<3; // takes about 580 ns
Sampledata.Rail_Feedback.m_Int =(AdcResult.ADCRESULT1)<<3; // takes about 580 ns
Sampledata.VIN_RECT.m_Int =(AdcResult.ADCRESULT2)<<3; // takes about 580 ns
//GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear ADCINT1 flag reinitialize for next SOC - takes 540 ns
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Acknowledge interrupt to PIE - takes 240 ns
GpioDataRegs.GPACLEAR.bit.GPIO10 = 1;
return;
}
My programm is running from Flash.
remark: This is not my first project with this processor.
I already set up a multi kW active PFC. There i collect ADC data from 2 ADCs, calculate 32Bit Type-2 controlers (in assembler) and set new PWM values in an EOC Interrupt within 2µs. So i think i probably missed something somewhere, maybe you can give me a hint in the right direction.
Thank you!
