TMS320F28075: PWM output pull-up after clearing OST trip

Brian Wang0

Part Number: TMS320F28075

Hi team,

I am supporting my customer testing their system protection function. Basically, they are testing to pull high with a OST trip and then recover the normal after clearing the OST flag.

However, there is a 10% opportunity that all the PWM channel would output a preiod of LOW state instead of normal PWM waveform.

The PWM intialization is as attached text file while the PWM disable/enable function is as the following picture.

Fullscreen PWM配置.txt Download

void InitSetPWM(void)
{//fk20140121
	DisableDrive();//fk20140123
	EALLOW;
	/////////////PWM1//////////////
//Set the Time-Base (TB) Module
	EPwm1Regs.TBPRD = C_INIT_PRD; 
	EPwm1Regs.CMPB = EPwm1Regs.TBPRD - gADC.DelayApply;
	EPwm1Regs.TBPHS.all = 0;
	EPwm1Regs.TBCTL.all = 0xE012;
    //EPwm1Regs.TBCTL.bit.FREE_SOFT = 3;
	//EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	//EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
	//EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;	//��ʱ���������ͬ���ź�
	EPwm1Regs.TBCTL.bit.HSPCLKDIV = PWM_CLK_DIV;
	//EPwm1Regs.TBCTL.bit.PHSDIR = TB_UP;
//Set the Counter-compare (CC) Module
	EPwm1Regs.CMPCTL.all = 0x0100;
	//EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	//EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	//EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
	//EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
	EPwm1Regs.CMPA.half.CMPA = C_INIT_PRD/2;
//Set the Action-qualifier (AQ) Module
	EPwm1Regs.AQCTLA.all = 0x0090;
	//EPwm1Regs.AQCTLA.bit.CAD = AQ_SET;
	//EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//Set the Dead-Band Generator (DB) Module
	EPwm1Regs.AQSFRC.all  = 0x0;
	EPwm1Regs.AQCSFRC.all = 0x0;	
	EPwm1Regs.DBCTL.all = 0x0007;
	//EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	//EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; 
	EPwm1Regs.DBFED = C_MAX_DB;
	EPwm1Regs.DBRED = C_MAX_DB;
//Set the PWM-chopper (PC) Module
//Set the Trip-zone (TZ) Module

    EPwm1Regs.TZCTL.all = 0x0005;

//Set the Event-trigger (ET) Module	
	EPwm1Regs.ETCLR.bit.INT = 1;				//��������жϱ�־
	EPwm1Regs.ETSEL.all = 0x0F09;
	//EPwm1Regs.ETSEL.bit.INTEN = 1;
	//EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
	//EPwm1Regs.ETSEL.bit.SOCAEN = 1;
	//EPwm1Regs.ETSEL.bit.SOCASEL = ET_CTRD_CMPB;	//COMPAR_B���½������ADC
	EPwm1Regs.ETPS.all = 0x0101;
	//EPwm1Regs.ETPS.bit.INTPRD = 1;
	//EPwm1Regs.ETPS.bit.SOCAPRD = 1;				//ÿһ�¼����һ��AD
	//****************************//606test

	//if(TUNE_NULL == gGetParVarable.TuneType)
	//{

	    //EPwm1Regs.CMPCTL.bit.LOADAMODE = 2; //607test
	    //EPwm1Regs.CMPCTL.bit.LOADBMODE = 2;


		EPwm1Regs.ETSEL.bit.INTSEL = 3;//ET_CTR_PRDZERO;//ET_CTR_PRDZERO;    // Select INT on Zero event //606test
	        EPwm1Regs.ETSEL.bit.INTEN = 1;               // Enable INT
	        EPwm1Regs.ETPS.bit.INTPRD = 1;//ET_1ST;          // Generate INT on 3rd event

	        EPwm1Regs.ETSEL.bit.SOCBEN = 1;      // Enable SOC on A group
	        EPwm1Regs.ETSEL.bit.SOCBSEL = 3;  // Select SOC from CMPA on
	                                                     // upcount
	        EPwm1Regs.ETPS.bit.SOCBPRD = 1;      // Generate pulse on every 3rd
	                                                     // event

	        EPwm1Regs.ETSEL.bit.SOCAEN = 1;      // Enable SOC on A group
	        EPwm1Regs.ETSEL.bit.SOCASEL = 3;  // Select SOC from CMPA on
	                                                     // upcount
	        EPwm1Regs.ETPS.bit.SOCAPRD = 1;      // Generate pulse on every 3rd
	//}
	/////////////PWM2//////////////
//Set the Time-Base (TB) Module
	EPwm2Regs.TBPRD = C_INIT_PRD; 
	EPwm2Regs.TBPHS.all = 0;
	EPwm2Regs.TBCTL.all = 0xE006;
    //EPwm2Regs.TBCTL.bit.FREE_SOFT = 3;
	//EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	//EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE;
	//EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;	//��PWM1ͬ���ź�Ϊ���ͬ���ź�
	EPwm2Regs.TBCTL.bit.HSPCLKDIV = PWM_CLK_DIV;
	//EPwm2Regs.TBCTL.bit.PHSDIR = TB_UP;
//Set the Counter-compare (CC) Module
	EPwm2Regs.CMPCTL.all = 0x0100;
	//EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	//EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	//EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
	//EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
	EPwm2Regs.CMPA.half.CMPA = C_INIT_PRD/2;
//Set the Action-qualifier (AQ) Module
	EPwm2Regs.AQCTLA.all = 0x0090;
	//EPwm2Regs.AQCTLA.bit.CAD = AQ_SET;
	//EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//Set the Dead-Band Generator (DB) Module
	EPwm2Regs.AQSFRC.all  = 0x0;
	EPwm2Regs.AQCSFRC.all = 0x0;	
	EPwm2Regs.DBCTL.all = 0x0007;
	//EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	//EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; 
	EPwm2Regs.DBFED = C_MAX_DB;
	EPwm2Regs.DBRED = C_MAX_DB;
//Set the PWM-chopper (PC) Module
//Set the Trip-zone (TZ) Module

    EPwm2Regs.TZCTL.all = 0x0005;
    EPwm2Regs.TZEINT.all = 0x0004;

//Set the Event-trigger (ET) Module	
    EPwm2Regs.ETSEL.all = 0;
    EPwm2Regs.ETPS.all  = 0;
    
   // if(TUNE_NULL == gGetParVarable.TuneType)
    //	{
       	 //   EPwm2Regs.CMPCTL.bit.LOADAMODE = 2;
    	 //   EPwm2Regs.CMPCTL.bit.LOADBMODE = 2;
    //	}
	/////////////PWM3//////////////
//Set the Time-Base (TB) Module
	EPwm3Regs.TBPRD = C_INIT_PRD;
	EPwm3Regs.TBPHS.all = 0;
	EPwm3Regs.TBCTL.all = 0xE036;
    //EPwm3Regs.TBCTL.bit.FREE_SOFT = 3;
	//EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
	//EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE;
	//EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
	//EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_DISABLE;	//������ͬ���ź�
	EPwm3Regs.TBCTL.bit.HSPCLKDIV = PWM_CLK_DIV;
	//EPwm3Regs.TBCTL.bit.PHSDIR = TB_UP;
//Set the Counter-compare (CC) Module
	EPwm3Regs.CMPCTL.all = 0x0100;
	//EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
	//EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
	//EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
	//EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
	EPwm3Regs.CMPA.half.CMPA = C_INIT_PRD/2;
//Set the Action-qualifier (AQ) Module
	EPwm3Regs.AQCTLA.all = 0x0090;
	//EPwm3Regs.AQCTLA.bit.CAD = AQ_SET;
	//EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;
//Set the Dead-Band Generator (DB) Module
	EPwm3Regs.AQSFRC.all  = 0x0;
	EPwm3Regs.AQCSFRC.all = 0x00;
	EPwm3Regs.DBCTL.all = 0x0007;
	//EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
	//EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; 
	EPwm3Regs.DBFED = C_MAX_DB;
	EPwm3Regs.DBRED = C_MAX_DB;

	//if(TUNE_NULL == gGetParVarable.TuneType)
	//    	{
	    	//    EPwm3Regs.CMPCTL.bit.LOADAMODE = 2;//CC_CTR_ZERO_PRD;
	    	//    EPwm3Regs.CMPCTL.bit.LOADBMODE = 2;//CC_CTR_ZERO_PRD;
	//    	}

    EPwm3Regs.TZCTL.all = 0x0005;
    EPwm3Regs.TZEINT.all = 0x0004;


//Set the Event-trigger (ET) Module	
	EDIS;
}

Obviously this all low output would threat customer's system safety(customer is using an inverted input gate driver). Comments are welcomed.

Regards,

Brian

over 5 years ago

0 Subrahmanya over 5 years ago

TI__Mastermind 24095 points

Hi,

The unexpected LOW states seem to be active for multiple PWM cycles. Is that correct?
If so, what is the causing the PWM to stay low? Is the PWM on and timer counting?
Once the OST flag is cleared PWM should resume normally.
Given that the PWM continues to stay low, there is some other event in the system or software holding it low.
It would be good to check the following -
- is the Trip input still active after clearing OST?
- Is the OST flag cleared (check in debugger or software read)
- Is the counter counting and register configuration is as expected?
Please debug and provide additional details, clearly something else in the system is holding PWMs low.

0 Brian Wang0 over 5 years ago in reply to Subrahmanya

TI__Expert 5400 points

Subrahmanya said:

Hi,

The unexpected LOW states seem to be active for multiple PWM cycles. Is that correct?

[Brian]: Yes, it keeps for multiple cycles.

If so, what is the causing the PWM to stay low? Is the PWM on and timer counting?

[Brian]: Actually this is the main problem. What customr did when PWM turn low is they called enabledriver() function; PWM keeps counting when PWM is disabled.

Once the OST flag is cleared PWM should resume normally.
Given that the PWM continues to stay low, there is some other event in the system or software holding it low.
It would be good to check the following -
- is the Trip input still active after clearing OST?
- Is the OST flag cleared (check in debugger or software read)
- Is the counter counting and register configuration is as expected?
Please debug and provide additional details, clearly something else in the system is holding PWMs low.

[Brian]: Working on confirming register status. The difficulty is it only lasts for several useconds, it would be hard to capture through CCS. Any idea how to better identify the root cause?

0 Subrahmanya over 5 years ago in reply to Brian Wang0

TI__Mastermind 24095 points

Hi,

Brian Wang0 said:
[Brian]: Working on confirming register status. The difficulty is it only lasts for several useconds, it would be hard to capture through CCS. Any idea how to better identify the root cause?

You can check the following.
- if i see the EnableDrive function, OST is being enabled and cleared and interrupt is also enabled. So, after clearing is it possible to check if the flag is getting set again? Is the Interrupt occurring? If so, it means that the trip input is still active and that could be holding the PWM output low for longer duration than expected.

0 Subrahmanya over 5 years ago in reply to Subrahmanya

TI__Mastermind 24095 points

Hi,

Did you get a chance to check the above? Is the issue resolved? Please update if you've any open questions.

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TMS320F28075: PWM output pull-up after clearing OST trip