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TMS320F280049C: Flagging/clearing of SCI errors in FIFO mode

Hong En Chew
Prodigy 170 points
Part Number: TMS320F280049C

Hi,

Would like to understand how SCI errors are flagged/cleared when in FIFO mode (SCIFFTX:SCIFFENA = 1) as the TRM is not clear on several points.

  1. When FIFO is enabled, is it correct to say that there 4 relevant errors and 5 error flags that can be set?
    Error Error flag(s) set when error occurs
    Break SCIRXST:RXERROR and SCIRXST:BRKDT
    Framing SCIRXBUF:SCIFFFE
    Parity SCIRXBUF:SCIFFPE
    Overrun SCIFFRX:RXFFOVF

  2. Is it correct to say that in FIFO mode only a Break error can trigger a receive interrupt (whereas Framing, Parity, and Overrun errors only set flags that must be checked manually in the receive ISR)? And for that to happen SCICTL1:RXERRINTENA must be set?

  3. Will the FE, OE, and PE error flags in SCIRXST be set by the hardware even when FIFO is enabled? i.e. causing the RXERROR flag to be set unnecessarily.

  4. Are the SCIFFFE and SCIFFPE error flags cleared by a software reset (SCICTL1:SWRESET) or channel reset (SCIFFTX:SCIRST)? Or can they only be cleared by writing zero to the flag directly?

Thank you!

Regards,

Hong En

  • 0
    TI__Genius 17315 points

    Hong,

    1. Your table looks correct.

     

    2. No, if RXERRINTENA is enabled the interrupt will automatically be triggered.  Note for BRKDT to generate an interrupt, RXBKINTENA must be enabled.

     

    3. Yes, these bits are independent of the FIFO being enabled.  The RXERROR flag is set by the logical OR of BRKDT, FE, OE, and PE.  Note that RXERROR would not be set unnecessarily, but if it did detect an error it would indicate that.

     

    4. These bits are only applicable when the FIFO is enabled.  Yes, both resets will clear these flags.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • 0 in reply to Ken Schachter
    Prodigy 170 points

    Hi Ken,

    Thanks for your reply, though I'm not clear on 2 & 4:

    2. To detect BRKDT errors, I was trying to use RXERRINTENA to enable interrupts as per footnote (2) of Table 23-4 in the TRM. The issue as you noted in your reply to Q3 is that FE, PE and OE (even though not relevant when FIFO is enabled) will also set the same RXERR flag and trigger the interrupt.

    The difficulty I'm facing is that upon a break error, FE is set first and BRKDT is only set 10 bit times after that. Is it correct to say that if I clear FE via a SCI software reset before BRKDT is set (i.e. before 10 bit times are up), BRKDT will never be set? Would like to know from TI what the expected behavior should be in order to write my error handling code.

    4. I've been unable to clear SCIFFFE/SCIFFPE flags with either of those two resets. Is there any way to do so?

    Regards,

    Hong En

  • 0 in reply to Hong En Chew
    TI__Genius 17315 points

    Hong,

    I am in the process of investigating your questions and I will reply soon.

    - Ken

  • 0 in reply to Ken Schachter
    Prodigy 170 points

    Thanks Ken, much appreciated.

  • 0 in reply to Hong En Chew
    TI__Genius 17315 points

    Hong,

    I consulted with the design team and below please find the reply to questions 2 and 4:

    2. FE is cleared by SCI software reset SWRESET bit, which resets the SCI state machine. So if FE is cleared before BRKDT is set , BRKDT will not get set after the software reset. Also, BRKDT clear should always be a part of error handling ISR.  There is a similar e2e query :

    https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/655383

     

    4. As per the register description of the SCIRXBUF (bit 15 SCIFFFE and bit 14 SCIFFPE) will be cleared by a system reset.

     

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

     

     

  • 0 in reply to Ken Schachter
    Prodigy 170 points

    Thanks Ken, appreciate the help.

    Regards,

    Hong En