CCS/LAUNCHXL-F28069M: Flash Mapping Problem (SCI)

Troodon

Part Number: LAUNCHXL-F28069M
Other Parts Discussed in Thread: C2000WARE

Tool/software: Code Composer Studio

Hello all,

I have created a program which is communicating with an E²PROM via I²C and PC via SCI. When Launchxl is first energized, it reads from E²PROM and writes the values to my parameters. Then with my pc interface, I can read these values or change these (write to Launchxl).

But this only works on debug mode perfectly.

When I does not start debug mode via ccs and only conect Launchxl to pc's usb, as I understand, sci is not working. But other functions are ok. Eeprom is answering the attend, launchxl gets the retentive values, I can even trigger ePWM.

Sci signal is being received but Launchxl does not understand the command.

I cannot always start the debug mode. As I understand, my FLASH map is not included sci. I could not understand that part good enough actually.

My FLASH map is given below.

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
/*
   RAML0       : origin = 0x008000, length = 0x000800
   RAML1       : origin = 0x008800, length = 0x000400
*/

   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

	FLASH		: origin = 0x3D8000, length = 0x018000
	RAM			: origin = 0x008000, length = 0x00C000

/*
   FLASHH      : origin = 0x3D8000, length = 0x004000
   FLASHG      : origin = 0x3DC000, length = 0x004000
   FLASHF      : origin = 0x3E0000, length = 0x004000
   FLASHE      : origin = 0x3E4000, length = 0x004000
   FLASHD      : origin = 0x3E8000, length = 0x004000
   FLASHC      : origin = 0x3EC000, length = 0x004000
*/

   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD860, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

	SYSRAM			: origin = 0x000000, length = 0x000800

/*
   BOOT_RSVD   : origin = 0x000000, length = 0x000050
   RAMM0       : origin = 0x000050, length = 0x0003B0
   RAMM1       : origin = 0x000400, length = 0x000400
*/


/*
   RAML2       : origin = 0x008C00, length = 0x000400
   RAML3       : origin = 0x009000, length = 0x001000
   RAML4       : origin = 0x00A000, length = 0x002000
   RAML5       : origin = 0x00C000, length = 0x002000
   RAML6       : origin = 0x00E000, length = 0x002000
   RAML7       : origin = 0x010000, length = 0x002000
   RAML8       : origin = 0x012000, length = 0x002000
*/

   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{
   /* Allocate program areas: */
   .cinit              : > FLASH,     	PAGE = 0
   .pinit              : > FLASH,     	PAGE = 0
   .text               : > FLASH,     	PAGE = 0
   codestart           : > BEGIN,      	PAGE = 0
/*
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
						 LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0
*/
   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitalized data sections: */
   .stack              : > SYSRAM,      PAGE = 1
   .ebss               : > RAM,      	PAGE = 0
   .esysmem            : > RAM,      	PAGE = 0

   /* Initalized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASH,     PAGE = 0
   .switch             : > FLASH,     PAGE = 0

   GROUP
    {
    	.TI.ramfunc
    	ramfuncs{
    	rts2800_fpu32.lib<fs_div.obj>(.text)
    	}
    	dclfuncs
    }    LOAD = FLASH,
         RUN = RAM,
         PAGE = 0,
         TABLE(BINIT)

   .binit : palign=0x8, fill=0xffff > FLASH

   /* Allocate IQ math areas: */
   IQmath              : > FLASH,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   /*
   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1
   */

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT


}

It is a modified version of F28069.cmd. The normal F28069.cmd does not work properly for me but this one was perfect except sci.

I have checked Example_2806xFlash, Example_2806xFlashProgramming, f28069_sci_flash_kernel but could understand their purpuse or if they are related.

What should I do exactly? If I should give more details, lead me, please.

Thank you.

P.S : S1 DIP switches are all 1 (H) on LaunchXL-F28069M. JP6 is not connected and JP7 is connected. I have worked that way until now.

over 6 years ago

0 Kevin Allen18 over 6 years ago

TI__Mastermind 45606 points

Hi Troodon,

Depending on your application code you may need to copy the SCI functions and ISRs from Flash to RAM and configure them properly to run from RAM. Please see the post below for more info:

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/758797

Best,

Kevin

0 Troodon over 6 years ago in reply to Kevin Allen18

Intellectual 615 points

Hello Kevin,

Thank you for your answer.

I think I have done quite much about "Running an Application from Internal Flash Memory" but maybe I am missing something.

I have changed my cmd files. Cmd files and usDelay.asm file are now as below.

Fullscreen FLASH.txt Download

/*
// TI File $Revision: /main/3 $
// Checkin $Date: March 3, 2011   13:45:53 $
//###########################################################################
//
// FILE:    F28069.cmd
//
// TITLE:   Linker Command File For F28069 Device
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Thu Oct 18 15:47:20 CDT 2018 $
// $Copyright:
// Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
//
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/

/* ======================================================
// For Code Composer Studio V2.2 and later
// ---------------------------------------
// In addition to this memory linker command file,
// add the header linker command file directly to the project.
// The header linker command file is required to link the
// peripheral structures to the proper locations within
// the memory map.
//
// The header linker files are found in <base>\headers\cmd
//
// For BIOS applications add:      F2806x_Headers_BIOS.cmd
// For nonBIOS applications add:   F2806x_Headers_nonBIOS.cmd
========================================================= */

/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l F2806x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l F2806x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\headers\cmd to the
   library search path under project->build options, linker tab,
   library search path (-i).
/*========================================================= */

/* Define the memory block start/length for the F2806x
   PAGE 0 will be used to organize program sections
   PAGE 1 will be used to organize data sections

   Notes:
         Memory blocks on F28069 are uniform (ie same
         physical memory) in both PAGE 0 and PAGE 1.
         That is the same memory region should not be
         defined for both PAGE 0 and PAGE 1.
         Doing so will result in corruption of program
         and/or data.

         Contiguous SARAM memory blocks can be combined
         if required to create a larger memory block.
*/

MEMORY
{
PAGE 0 :   /* Program Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   RAML0       : origin = 0x008000, length = 0x000800     /* on-chip RAM block L0 */
   RAML1       : origin = 0x008800, length = 0x000400     /* on-chip RAM block L1 */
   OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */

   FLASHH      : origin = 0x3D8000, length = 0x004000     /* on-chip FLASH */
   FLASHG      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
   FLASHF      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
   FLASHE      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
   FLASHD      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
   FLASHC      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
   FLASHA      : origin = 0x3F4000, length = 0x003F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
   CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

   FPUTABLES   : origin = 0x3FD590, length = 0x0006A0	  /* FPU Tables in Boot ROM */
   IQTABLES    : origin = 0x3FDF00, length = 0x000B50     /* IQ Math Tables in Boot ROM */
   IQTABLES2   : origin = 0x3FEA50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
   IQTABLES3   : origin = 0x3FEADC, length = 0x0000AA	  /* IQ Math Tables in Boot ROM */

   ROM         : origin = 0x3FF3B0, length = 0x000C10     /* Boot ROM */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 :   /* Data Memory */
           /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
           /* Registers remain on PAGE1                                                  */

   BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
   RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   RAML2       : origin = 0x008C00, length = 0x000400     /* on-chip RAM block L2 */
   RAML3       : origin = 0x009000, length = 0x001000	  /* on-chip RAM block L3 */
   RAML4       : origin = 0x00A000, length = 0x002000     /* on-chip RAM block L4 */
   RAML5       : origin = 0x00C000, length = 0x002000     /* on-chip RAM block L5 */
   RAML6       : origin = 0x00E000, length = 0x002000     /* on-chip RAM block L6 */
   RAML7       : origin = 0x010000, length = 0x002000     /* on-chip RAM block L7 */
   RAML8       : origin = 0x012000, length = 0x002000     /* on-chip RAM block L8 */
   USB_RAM     : origin = 0x040000, length = 0x000800     /* USB RAM		  */
   FLASHB      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
}

/* Allocate sections to memory blocks.
   Note:
         codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                   execution when booting to flash
         ramfuncs  user defined section to store functions that will be copied from Flash into RAM
*/


SECTIONS
{

   /* Allocate program areas: */
   .cinit              : > FLASHA,     PAGE = 0
   .pinit              : > FLASHA,     PAGE = 0
   .text               : > FLASHA,     PAGE = 0
   codestart           : > BEGIN,      PAGE = 0
   ramfuncs            : LOAD = FLASHD,
                         RUN = RAML0,
                         LOAD_START(_RamfuncsLoadStart),
                         LOAD_END(_RamfuncsLoadEnd),
                         RUN_START(_RamfuncsRunStart),
						 LOAD_SIZE(_RamfuncsLoadSize),
                         PAGE = 0

   csmpasswds          : > CSM_PWL_P0, PAGE = 0
   csm_rsvd            : > CSM_RSVD,   PAGE = 0

   /* Allocate uninitialized data sections: */
   .stack              : > RAMM0,      PAGE = 1
   .ebss               : > RAML4,      PAGE = 1
   .esysmem            : > RAML2,      PAGE = 1
   .cio                : > RAML5,      PAGE = 1

   /* Initialized sections to go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst             : > FLASHA,     PAGE = 0
   .switch             : > FLASHA,     PAGE = 0

   /* Allocate IQ math areas: */
   IQmath              : > FLASHA,     PAGE = 0            /* Math Code */
   IQmathTables        : > IQTABLES,   PAGE = 0, TYPE = NOLOAD

   /* Allocate FPU math areas: */
   FPUmathTables       : > FPUTABLES,  PAGE = 0, TYPE = NOLOAD

   DMARAML5	           : > RAML5,      PAGE = 1
   DMARAML6	           : > RAML6,      PAGE = 1
   DMARAML7	           : > RAML7,      PAGE = 1
   DMARAML8	           : > RAML8,      PAGE = 1

  /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
    /* Uncomment the section below if calling the IQNasin() or IQasin()
       functions from the IQMath.lib library in order to utilize the
       relevant IQ Math table in Boot ROM (This saves space and Boot ROM
       is 1 wait-state). If this section is not uncommented, IQmathTables2
       will be loaded into other memory (SARAM, Flash, etc.) and will take
       up space, but 0 wait-state is possible.
    */
    /*
    IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
    {

               IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

    }
    */

   /* .reset is a standard section used by the compiler.  It contains the */
   /* the address of the start of _c_int00 for C Code.   /*
   /* When using the boot ROM this section and the CPU vector */
   /* table is not needed.  Thus the default type is set here to  */
   /* DSECT  */
   .reset              : > RESET,      PAGE = 0, TYPE = DSECT
   vectors             : > VECTORS,    PAGE = 0, TYPE = DSECT

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen Headers nonBIOS.txt Download

/*
//###########################################################################
//
// FILE:    F2806x_Headers_nonBIOS.cmd
//
// TITLE:   F2806x Peripheral registers linker command file
//
// DESCRIPTION:
//
//          This file is for use in Non-BIOS applications.
//
//          Linker command file to place the peripheral structures
//          used within the F2806x headerfiles into the correct memory
//          mapped locations.
//
//          This version of the file includes the PieVectorTable structure.
//          For BIOS applications, please use the F2806x_Headers_BIOS.cmd file
//          which does not include the PieVectorTable structure.
//
//###########################################################################
// $TI Release: F2806x Support Library v2.04.00.00 $
// $Release Date: Thu Oct 18 15:47:20 CDT 2018 $
// $Copyright:
// Copyright (C) 2009-2018 Texas Instruments Incorporated - http://www.ti.com/
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
//
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the
//   distribution.
//
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
*/

MEMORY
{
 PAGE 0:    /* Program Memory */

 PAGE 1:    /* Data Memory */

      DEV_EMU     : origin = 0x000880, length = 0x000105     /* Device Emulation Registers */
      SYS_PWR_CTL : origin = 0x000985, length = 0x000003     /* System Power Control Registers */
      FLASH_REGS  : origin = 0x000A80, length = 0x000060     /* Flash Registers */
      CSM         : origin = 0x000AE0, length = 0x000020     /* Code Security Module Registers */

      ADC_RESULT  : origin = 0x000B00, length = 0x000020     /* ADC Results Register Mirror */

      CPU_TIMER0  : origin = 0x000C00, length = 0x000008     /* CPU Timer0 Registers */
      CPU_TIMER1  : origin = 0x000C08, length = 0x000008     /* CPU Timer1 Registers */
      CPU_TIMER2  : origin = 0x000C10, length = 0x000008     /* CPU Timer2 Registers */

      PIE_CTRL    : origin = 0x000CE0, length = 0x000020     /* PIE Control Registers */
      PIE_VECT    : origin = 0x000D00, length = 0x000100     /* PIE Vector Table */

      DMA	      : origin = 0x001000, length = 0x000200     /* DMA Registers */

      CLA1        : origin = 0x001400, length = 0x000080     /* CLA Registers */

      USB0	      : origin = 0x004000, length = 0x001000     /* USB0 Registers */

      McBSPA      : origin = 0x005000, length = 0x000040     /* McBSP-A Registers */

      ECANA       : origin = 0x006000, length = 0x000040     /* eCAN-A Control and Status Registers */
      ECANA_LAM   : origin = 0x006040, length = 0x000040     /* eCAN-A Local Acceptance Masks */
      ECANA_MOTS  : origin = 0x006080, length = 0x000040     /* eCAN-A Message Object Time Stamps */
      ECANA_MOTO  : origin = 0x0060C0, length = 0x000040     /* eCAN-A Object Time-Out Registers */
      ECANA_MBOX  : origin = 0x006100, length = 0x000100     /* eCAN-A Milboxes */

      COMP1       : origin = 0x006400, length = 0x000020     /* Comparator + DAC 1 Registers */
      COMP2       : origin = 0x006420, length = 0x000020     /* Comparator + DAC 2 Registers */
      COMP3       : origin = 0x006440, length = 0x000020     /* Comparator + DAC 3 Registers */

      EPWM1       : origin = 0x006800, length = 0x000040     /* Enhanced PWM 1 Registers */
      EPWM2       : origin = 0x006840, length = 0x000040     /* Enhanced PWM 2 Registers */
      EPWM3       : origin = 0x006880, length = 0x000040     /* Enhanced PWM 3 Registers */
      EPWM4       : origin = 0x0068C0, length = 0x000040     /* Enhanced PWM 4 Registers */
      EPWM5       : origin = 0x006900, length = 0x000040     /* Enhanced PWM 5 Registers */
      EPWM6       : origin = 0x006940, length = 0x000040     /* Enhanced PWM 6 Registers */
      EPWM7       : origin = 0x006980, length = 0x000040     /* Enhanced PWM 7 Registers */
      EPWM8       : origin = 0x0069C0, length = 0x000040     /* Enhanced PWM 8 Registers */

      ECAP1       : origin = 0x006A00, length = 0x000020     /* Enhanced Capture 1 Registers */
      ECAP2       : origin = 0x006A20, length = 0x000020     /* Enhanced Capture 2 Registers */
      ECAP3       : origin = 0x006A40, length = 0x000020     /* Enhanced Capture 3 Registers */

   	  HRCAP1      : origin = 0x006AC0, length = 0x000020	 /* High Resolution Capture 1 Registers */
   	  HRCAP2      : origin = 0x006AE0, length = 0x000020     /* High Resolution Capture 2 Registers */

      EQEP1       : origin = 0x006B00, length = 0x000040     /* Enhanced QEP 1 Registers */
      EQEP2       : origin = 0x006B40, length = 0x000040     /* Enhanced QEP 2 Registers */

      HRCAP3	  : origin = 0x006C80, length = 0x000020	 /* High Resolution Capture 3 Registers */
      HRCAP4	  : origin = 0x006CA0, length = 0x000020	 /* High Resolution Capture 4 Registers */

      GPIOCTRL    : origin = 0x006F80, length = 0x000040     /* GPIO Control Registers */
      GPIODAT     : origin = 0x006FC0, length = 0x000020     /* GPIO Data Registers */
      GPIOINT     : origin = 0x006FE0, length = 0x000020     /* GPIO Interrupt/LPM Registers */

      SYSTEM      : origin = 0x007010, length = 0x000030     /* System Control Registers */

      SPIA        : origin = 0x007040, length = 0x000010     /* SPI-A Registers */
      SPIB        : origin = 0x007740, length = 0x000010     /* SPI-B Registers */

      SCIA        : origin = 0x007050, length = 0x000010     /* SCI-A Registers */
      SCIB	      : origin = 0x007750, length = 0x000010     /* SCI-B Registers */

      NMIINTRUPT  : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */
      XINTRUPT    : origin = 0x007070, length = 0x000010     /* External Interrupt Registers */

      ADC         : origin = 0x007100, length = 0x000080     /* ADC Registers */

      I2CA        : origin = 0x007900, length = 0x000040     /* I2C-A Registers */

      PARTID      : origin = 0x3D7E80, length = 0x000001     /* Part ID Register Location */

      CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA CSM password locations */
}


SECTIONS
{
/*** PIE Vect Table and Boot ROM Variables Structures ***/
  UNION run = PIE_VECT, PAGE = 1
   {
      PieVectTableFile
      GROUP
      {
         EmuKeyVar
         EmuBModeVar
         FlashCallbackVar
         FlashScalingVar
      }
   }

/*** Peripheral Frame 0 Register Structures ***/
   DevEmuRegsFile    : > DEV_EMU,     PAGE = 1
   SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
   FlashRegsFile     : > FLASH_REGS,  PAGE = 1
   CsmRegsFile       : > CSM,         PAGE = 1
   AdcResultFile     : > ADC_RESULT,  PAGE = 1
   CpuTimer0RegsFile : > CPU_TIMER0,  PAGE = 1
   CpuTimer1RegsFile : > CPU_TIMER1,  PAGE = 1
   CpuTimer2RegsFile : > CPU_TIMER2,  PAGE = 1
   PieCtrlRegsFile   : > PIE_CTRL,    PAGE = 1
   Cla1RegsFile      : > CLA1,        PAGE = 1
   DmaRegsFile       : > DMA,	      PAGE = 1

/*** Peripheral Frame 1 Register Structures ***/
   ECanaRegsFile     : > ECANA,       PAGE = 1
   ECanaLAMRegsFile  : > ECANA_LAM,   PAGE = 1
   ECanaMboxesFile   : > ECANA_MBOX,  PAGE = 1
   ECanaMOTSRegsFile : > ECANA_MOTS,  PAGE = 1
   ECanaMOTORegsFile : > ECANA_MOTO,  PAGE = 1
   ECap1RegsFile     : > ECAP1,       PAGE = 1
   ECap2RegsFile     : > ECAP2,       PAGE = 1
   ECap3RegsFile     : > ECAP3,       PAGE = 1
   EQep1RegsFile     : > EQEP1,       PAGE = 1
   EQep2RegsFile     : > EQEP2,       PAGE = 1
   GpioCtrlRegsFile  : > GPIOCTRL,    PAGE = 1
   GpioDataRegsFile  : > GPIODAT,     PAGE = 1
   GpioIntRegsFile   : > GPIOINT,     PAGE = 1
   HRCap1RegsFile    : > HRCAP1, 	  PAGE = 1
   HRCap2RegsFile    : > HRCAP2,      PAGE = 1
   HRCap3RegsFile    : > HRCAP3, 	  PAGE = 1
   HRCap4RegsFile    : > HRCAP4, 	  PAGE = 1

/*** Peripheral Frame 2 Register Structures ***/
   SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
   SpiaRegsFile      : > SPIA,        PAGE = 1
   SpibRegsFile      : > SPIB,        PAGE = 1
   SciaRegsFile      : > SCIA,        PAGE = 1
   ScibRegsFile      : > SCIB, 	      PAGE = 1
   NmiIntruptRegsFile: > NMIINTRUPT,  PAGE = 1
   XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
   AdcRegsFile       : > ADC,         PAGE = 1
   I2caRegsFile      : > I2CA,        PAGE = 1

/*** Peripheral Frame 3 Register Structures ***/
   Comp1RegsFile     : > COMP1,    PAGE = 1
   Comp2RegsFile     : > COMP2,    PAGE = 1
   Comp3RegsFile     : > COMP3,    PAGE = 1
   EPwm1RegsFile     : > EPWM1,    PAGE = 1
   EPwm2RegsFile     : > EPWM2,    PAGE = 1
   EPwm3RegsFile     : > EPWM3,    PAGE = 1
   EPwm4RegsFile     : > EPWM4,    PAGE = 1
   EPwm5RegsFile     : > EPWM5,    PAGE = 1
   EPwm6RegsFile     : > EPWM6,    PAGE = 1
   EPwm7RegsFile     : > EPWM7,    PAGE = 1
   EPwm8RegsFile     : > EPWM8,    PAGE = 1
   McbspaRegsFile    : > McBSPA,   PAGE = 1
   Usb0RegsFile		 : > USB0,     PAGE = 1

/*** Code Security Module Register Structures ***/
   CsmPwlFile        : > CSM_PWL,  PAGE = 1

/*** Device Part ID Register Structures ***/
   PartIdRegsFile    : > PARTID,   PAGE = 1

}

/*
//===========================================================================
// End of file.
//===========================================================================
*/

Fullscreen usDelay.txt Download

;//###########################################################################
;//
;// FILE:  F2806x_usDelay.asm
;//
;// TITLE: Simple delay function
;//
;// DESCRIPTION:
;//
;// This is a simple delay function that can be used to insert a specified
;// delay into code.
;//
;// This function is only accurate if executed from internal zero-waitstate
;// SARAM. If it is executed from waitstate memory then the delay will be
;// longer then specified.
;//
;// To use this function:
;//
;//  1 - update the CPU clock speed in the F2806x_Examples.h
;//    file. For example:
;//    #define CPU_RATE 12.500L // for an 80MHz CPU clock speed
;//
;//  2 - Call this function by using the DELAY_US(A) macro
;//    that is defined in the F2806x_Examples.h file.  This macro
;//    will convert the number of microseconds specified
;//    into a loop count for use with this function.
;//    This count will be based on the CPU frequency you specify.
;//
;//  3 - For the most accurate delay
;//    - Execute this function in 0 waitstate RAM.
;//    - Disable interrupts before calling the function
;//      If you do not disable interrupts, then think of
;//      this as an "at least" delay function as the actual
;//      delay may be longer.
;//
;//  The C assembly call from the DELAY_US(time) macro will
;//  look as follows:
;//
;//  extern void Delay(long LoopCount);
;//
;//        MOV   AL,#LowLoopCount
;//        MOV   AH,#HighLoopCount
;//        LCR   _Delay
;//
;//  Or as follows (if count is less then 16-bits):
;//
;//        MOV   ACC,#LoopCount
;//        LCR   _Delay
;//
;//
;//###########################################################################
;// $TI Release: F2806x C/C++ Header Files and Peripheral Examples V151 $
;// $Release Date: February  2, 2016 $
;// $Copyright: Copyright (C) 2011-2016 Texas Instruments Incorporated -
;//             http://www.ti.com/ ALL RIGHTS RESERVED $
;//###########################################################################

;//
;//  *IMPORTANT*
;//  IF RUNNING FROM FLASH, PLEASE COPY OVER THE SECTION "ramfuncs"  FROM FLASH
;//  TO RAM PRIOR TO CALLING InitSysCtrl(). THIS PREVENTS THE MCU FROM THROWING AN EXCEPTION
;//  WHEN A CALL TO DELAY_US() IS MADE.
;//
       .def _DSP28x_usDelay
       .sect "ramfuncs"

        .global  __DSP28x_usDelay
_DSP28x_usDelay:
        SUB    ACC,#1
        BF     _DSP28x_usDelay,GEQ    ;; Loop if ACC >= 0
        LRETR

;There is a 9/10 cycle overhead and each loop
;takes five cycles. The LoopCount is given by
;the following formula:
;  DELAY_CPU_CYCLES = 9 + 5*LoopCount
; LoopCount = (DELAY_CPU_CYCLES - 9) / 5
; The macro DELAY_US(A) performs this calculation for you
;
;//===========================================================================
;// End of file.
;//===========================================================================

Inside main, codes below are also added.

    memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (Uint32)&RamfuncsLoadSize);

// Call Flash Initialization to setup flash waitstates
// This function must reside in RAM

    InitFlash();    // Call the flash wrapper init function

But still, when I only plug the usb cable without CCS, LaunchXL does not work as it is on debug mode.

Is there a way to understand what is going on inside LaunchXL without being connected with debug mode? Is "CTRL+F8 Free Run" for this?

(I don't think so. Sci also works perfectly with Free Run. But not when I just plug the usb cable.)

I am trying to deal with this massive confusion at the moment. :))

Ok I will ask step by step.

Lets say I started a debug mode. Program works perfectly that way.

Then I removed the usb cable of LaunchXL. The debugger status would be like this.

I reinserted the usb cable. Then clicked on "Connect Target".

It said 0x3FF75B (no symbols are defined) and when I pressed F5 or F6 to see a progression step by step, adresses changed and finally it passed to CodeStartBranch.asm

wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB _c_int00         ;Branch to start of boot.asm in RTS library

    .endif

;end wd_disable

And then boot28.asm. There is a loop over there that goes on.

LOOP:
	MOVB    AH,#0		        ; zero out upper addr bits
	PREAD   AL,*XAR7		; load address of variable to be inited
	ADDB    XAR7,#1			; point to initialization data
       	B	GET_DATA,NTC	        ; get data if variable is not far 
	CLRC    TC		        ; reset TC bit used as far flag 
	PREAD   AH,*XAR7	        ; otherwise, get hi bits of 22-bit addr
	ADDB    XAR7,#1
GET_DATA:	
	MOVL	XAR6,ACC	        ; address
	RPT	AR1			; repeat length + 1 times
||	PREAD   *XAR6++,*XAR7		; copy data from table to memory
	
	MOVL	ACC,XAR7		; using ACC as temp, point XAR7 to 
	ADD  	ACC,AR1			; next cinit record since PREAD 
	ADDB	ACC,#1			; doesn't change value of XAR7. 
	MOVL	XAR7,ACC	
START:
	PREAD	AL,*XAR7		; load length
	B	GET_ADDR,GEQ	        ; a length < 0 denotes far data	 
        NEG     AL		        ; negate value to get real length	
	SETC    TC		        ; flag that the address field is 32-bits
GET_ADDR:	
	MOVZ	AR1,AL		        ; copy length value to loop register
        ADDB    XAR7,#1			; point to address field
	BANZ	LOOP,AR1--		; if (length-- != 0) continue

Unless I press the F8 (Resume) button, that loop goes on forever. If I press F8, sci works perfectly.

I think that is what happened when I only energize LaunchXL without connecting CCS debug mode?

Any idea what is going on over here?

0 Troodon over 6 years ago in reply to Troodon

Intellectual 615 points

Hello? :)

I just want serial communication interface to be run from flash without connecting with code composer studio. What should I do further according to my files?

0 Kevin Allen18 over 5 years ago in reply to Troodon

TI__Mastermind 45606 points

Hi Troodon,

Very sorry for the delay. Can you provide a screenshot of your project in the project explorer of CCS?

Maybe you're missing the file 'F2806x_CodeStartBranch.asm' located in C2000ware below:

C:\ti\c2000\C2000Ware_3_01_00_00\device_support\f2806x\common\source

Please see the example project in C2000ware below for an example that's run from flash in standalone.

C:\ti\c2000\C2000Ware_3_01_00_00\device_support\f2806x\examples\c28\flash_f28069

Your issue could be HW related as well. Please see the documented Boot Mode pin states in the device datasheet. Make sure you have the states correct for boot from Flash.

Best,

Kevin

0 Troodon over 5 years ago in reply to Kevin Allen18

Intellectual 615 points

Hello Kevin,

Project explorer screenshot is given below.

F2806x_CodeStartBranch.asm is also given below.

;// TI File $Revision: /main/2 $
;// Checkin $Date: January 4, 2011   10:10:05 $
;//###########################################################################
;//
;// FILE:  F2806x_CodeStartBranch.asm
;//
;// TITLE: Branch for redirecting code execution after boot.
;//
;// For these examples, code_start is the first code that is executed after
;// exiting the boot ROM code.
;//
;// The codestart section in the linker cmd file is used to physically place
;// this code at the correct memory location.  This section should be placed
;// at the location the BOOT ROM will re-direct the code to.  For example,
;// for boot to FLASH this code will be located at 0x3f7ff6.
;//
;// In addition, the example F2806x projects are setup such that the codegen
;// entry point is also set to the code_start label.  This is done by linker
;// option -e in the project build options.  When the debugger loads the code,
;// it will automatically set the PC to the "entry point" address indicated by
;// the -e linker option.  In this case the debugger is simply assigning the PC,
;// it is not the same as a full reset of the device.
;//
;// The compiler may warn that the entry point for the project is other then
;//  _c_init00.  _c_init00 is the C environment setup and is run before
;// main() is entered. The code_start code will re-direct the execution
;// to _c_init00 and thus there is no worry and this warning can be ignored.
;//
;//###########################################################################
;// $TI Release: F2806x Support Library v2.05.00.00 $
;// $Release Date: Thu Mar 19 07:33:23 IST 2020 $
;// $Copyright:
;// Copyright (C) 2009-2020 Texas Instruments Incorporated - http://www.ti.com/
;//
;// Redistribution and use in source and binary forms, with or without
;// modification, are permitted provided that the following conditions
;// are met:
;//
;//   Redistributions of source code must retain the above copyright
;//   notice, this list of conditions and the following disclaimer.
;//
;//   Redistributions in binary form must reproduce the above copyright
;//   notice, this list of conditions and the following disclaimer in the
;//   documentation and/or other materials provided with the
;//   distribution.
;//
;//   Neither the name of Texas Instruments Incorporated nor the names of
;//   its contributors may be used to endorse or promote products derived
;//   from this software without specific prior written permission.
;//
;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;// $
;//###########################################################################

***********************************************************************

WD_DISABLE	.set	1		;set to 1 to disable WD, else set to 0

    .ref _c_int00
    .global code_start

***********************************************************************
* Function: codestart section
*
* Description: Branch to code starting point
***********************************************************************

    .sect "codestart"

code_start:
    .if WD_DISABLE == 1
        LB wd_disable       ;Branch to watchdog disable code
    .else
        LB _c_int00         ;Branch to start of boot.asm in RTS library
    .endif

;end codestart section

***********************************************************************
* Function: wd_disable
*
* Description: Disables the watchdog timer
***********************************************************************
    .if WD_DISABLE == 1

    .text
wd_disable:
    SETC OBJMODE        ;Set OBJMODE for 28x object code
    EALLOW              ;Enable EALLOW protected register access
    MOVZ DP, #7029h>>6  ;Set data page for WDCR register
    MOV @7029h, #0068h  ;Set WDDIS bit in WDCR to disable WD
    EDIS                ;Disable EALLOW protected register access
    LB _c_int00         ;Branch to start of boot.asm in RTS library

    .endif

;end wd_disable

	.end

;//
;// End of file.
;//

Identical with "C:\ti\c2000\C2000Ware_3_01_00_00\device_support\f2806x\common\source"

When I am connected with CCS, the project works properly. Without CCS, when I remove the usb ang plug, it does not work. SCI is the problem.

I cannot connect it to ccs all the time. :)

I checked the boot mode pin states in the device datasheet:

3 DIP switches are all H.

Something similar happens with this topic.

https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/664624

As it is mentioned, when I press the reset button, it works.

I will enable the interrupt for errors on SCI-A RX, and reset SCI-A when they occurred.

Problem is solved, thank you. :)

C2000™︎ microcontrollers

C2000 microcontrollers forum

CCS/LAUNCHXL-F28069M: Flash Mapping Problem (SCI)