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CCS/TMS320F28388D: ERAD Module missing cycles

Quentin Van Straaten
Prodigy 160 points

Part Number: TMS320F28388D

Tool/software: Code Composer Studio

Hi,

I am currently experimenting with the Erad module embedded on the TMS320F28388D microcontroller. The technical reference manual is pretty clear and I managed to profile different code segments, interruptions and CLA tasks using both the Enhanced Bus Comparator (EBC) and the System Event Counter (SEC).

However, I still have 2 issues to adress:

- I am note quite sure what the virtual program counter is (p.1453). This is the only mention of this counter in the whole document. My guess is that it refers to a counter in the debbuger server managing the pipeline steps.

- I have a CLA task triggered by an ADC interrupt triggered by a SOC generated by a PWM module. The PWM clock is running at 200Mhz, it is running in up and down mode and it generates a 602,4KHz (checked on an oscilloscope) signal so TBPRD = 166 and the whole period lasts 332 cycles.The System clock is the same than the PWM module so 200Mhz. I use a SEC submodule to profile the latency between the ADC interruption signal and the beginning of the task, and another to count the clock cycle between the beginning of the task and the next ADC interruption signal. Theses two timespans are supposed to describe a whole period. Both SEC submodules runs in start stop mode so it feeds the MAX_COUNT registers. When I run them, the maximum count for the latency is 2 clock cycles and the maximum count for my other counter is 328 which sums up to 330 clock cycles. However my period last 332 clock cycles so 2 clock cycles are lost. Is this one per measure?

Switching from the MAX MODE COUNT and the CUMULATIVE MODE COUNT during my experimentations, I noted that the number of cycles stored in the MAX_COUNT registered could actually be the value - 1 but the technical reference manual does not mention it.

I aim improving my real time management and I believe the ERAD module will be of great help so I am trying to clear any doubts.

Regards,

Quentin

  • 0
    TI__Guru 52080 points

    1. VPC, virtual program counter, the program counter of the MCU. The register in an MCU that tells what the address (location) of the instruction being executed at the current time.

    2. You have to realize it counts from ZERO to 328. It seems correct.

  • 0 in reply to Nima Eskandari
    Prodigy 160 points

    Hi,

    Thanks for your quick reply.

     1. The technical reference manual states :

    "This is done through monitoring any of the program address buses, Virtual Program Counter (VPC), or the Program Counter of the CPU"

    So I am still confused as their seems to be a distinction between the Program Counter and the Virtual Program Counter. I try to understand the difference between the VPC options and the PAB option for the BUS_SEL field of the HWBP_CNTL register of the EBC submodule.

    2. Do you maybe have some chronogram highlighting the incrementation of the SEC counter in the different modes? (Max Mode count and Continuous Count)

  • 0 in reply to Quentin Van Straaten
    TI__Guru 52080 points

    I'll send you the descriptions.

  • 0 in reply to Nima Eskandari
    Prodigy 160 points

    Hi Nima,

    Did you find some time to look for the informations I asked for?

    Regards,

    Quentin

  • 0 in reply to Quentin Van Straaten
    TI__Guru 52080 points

    The counting depends on whether your are in EVENT mode or in normal mode. In event mode, as long as the counter is active (in the case of start-stop mode, the start condition has occured and the stop condition hasnt), the number of the rising edges. IF it is not in EVENT mode, the counter will just count up on as long as the counter is active (every rising edge of the clock).

    For PAB and PC, that is program-read address bus and the program counter. They are standard in realtime MCU.

    PAB —Program address bus. The PAB carries addresses for reads and writes from program space. PAB is a 22-bit bus.

    Program Counter (PC) -  When the pipeline is full, the 22-bit program counter (PC) always points to the instruction that is currently being processed — the instruction that has just reached the decode 2 phase of the pipeline. Once an instruction reaches this phase of the pipeline, it cannot be flushed from the pipeline by an interrupt. It is executed before the interrupt is taken.

    I have requested information about the VPC.

  • 0 in reply to Nima Eskandari
    TI__Guru 52080 points

    VPC is the same as PC as far as the ERAD module is concerned.

    PAB is the Program Address bus which fetches instructions from memory. The CPU has the notion of fetching ahead as much as it can to keep the instruction buffers full. There is no guarantee that something that is fetched will get executed. This is because an instruction that is fetched earlier could branch or there could be interrupts in between.

  • 0 in reply to Nima Eskandari
    Prodigy 160 points

    Hi Nima,

    Thanks again for all these informations.

    1. My point when asking about chronograms for the SEC incrementation is to understand if there is any delay induced by the Max Count Mode as I've observed a difference in the number of cycle measured in countinuous mode and the max count mode.

    2. About the VPC and the PAB, I am trying to understand at what stage of the pipeline my HWBP module will be triggered depeding on the BUS_SEL value of the HWBP_CNTL registers. 

    Here is the extract of the TMS320F2838x Microcontrollers Technical Reference Manual:

    "These bits are used to select which CPU buses will be used for
    comparison to generate the match events. For each bus selected,
    the corresponding strobes will automatically be selected to determine
    valid accesses.
    0000 PAB for instruction fetches
    0001 VPC
    0010 DWAB for data write accesses
    0011 DRAB for data read accesses
    0100 DWDB for write data match
    0101 DRDB for read data match
    0110 VPC Instruction aligned match
    0111 VPC R1 aligned match
    1000 VPC R2 aligned match
    1001 VPC W aligned match
    All other combinations are RESERVED."

    I have no problem for PAB, DWAB, DRAB, DWDB and DRDB. But what is the difference between VCP and VCP Insruction aligned match? From the informations you gave, I understand:

    0001 VPC -> generates an event when the instruction reaches D2 step in the pipeline

    0110 VPC Instruction aligned match -> ?

    0111 VPC R1 aligned match ->  generates an event when the instruction reaches R1 step in the pipeline

    0111 VPC R1 aligned match ->  generates an event when the instruction reaches R2 step in the pipeline

    0111 VPC W aligned match ->  generates an event when the instruction reaches W step in the pipeline

    Is this correct? 

     

    Regards,

    Quentin

  • 0 in reply to Quentin Van Straaten
    TI__Guru 52080 points

    I'm not sure about the instruction aligned. I will ask the designer and get back.

  • 0 in reply to Nima Eskandari
    TI__Guru 52080 points

    I should have an answer shortly.

  • 0 in reply to Nima Eskandari
    TI__Guru 52080 points

    Okay the answer I have is if you have this device, use the VPC Instruction aligned match instead of just "VPC".

    VPC is for backwards compatibility with the older devices. In some boundary conditions it could be inaccurate, so using the VPC aligned will ensure that an event is generated when the instruction reaches D2 step in the pipeline.