Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE, TMDSCNCD28379D
Tool/software: Code Composer Studio
I want to implement a 16 words FIFO with interrupt fro RX and TX,
I am using this code;
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#define CPU_FREQ 200E6 #define LSPCLK_FREQ CPU_FREQ/4 /* Default value at reset */ #define SCI_FREQ 115200 #define SCI_PRD ((LSPCLK_FREQ/(SCI_FREQ*8))-1) EALLOW; SciaRegs.SCICCR.all = 0x0007; // 1 stop bit, No loopback // No parity,8 char bits, // async mode, idle-line protocol /* Enable TX, RX, internal SCICLK */ SciaRegs.SCICTL1.all = 0x0003; // Disable RX ERR, SLEEP, TXWAKE SciaRegs.SCICTL2.bit.TXINTENA = 1; SciaRegs.SCICTL2.bit.RXBKINTENA = 1; SciaRegs.SCIHBAUD.all = ((uint16_t)SCI_PRD & 0xFF00U) >> 8U; SciaRegs.SCILBAUD.all = (uint16_t)SCI_PRD & 0x00FFU; /* FIFO configuration for Transmission * Set the maximum level for the FIFO interrupt */ SciaRegs.SCIFFTX.bit.TXFFIL = 0x10; /* Enable the interrupt for FIFO */ SciaRegs.SCIFFTX.bit.SCIFFENA = 1; /* Send when FIFO is full */ SciaRegs.SCIFFTX.bit.TXFFST = 0x10; /* Clear flag */ SciaRegs.SCIFFTX.bit.TXFFINTCLR = 1; /* Reset SCI */ SciaRegs.SCIFFTX.bit.SCIRST = 1; /* FIFO configuration for Reception * Set the maximum level for the FIFO interrupt */ SciaRegs.SCIFFRX.bit.RXFFIL = 0x10; /* Enable RX interrupt */ SciaRegs.SCIFFRX.bit.RXFFIENA = 1; /* Clear RX interrupt flag */ SciaRegs.SCIFFRX.bit.RXFFINTCLR = 1; SciaRegs.SCIFFCT.all = 0x00; SciaRegs.SCICTL1.all = 0x0023; // Relinquish SCI from Reset SciaRegs.SCIFFTX.bit.TXFIFORESET = 1; SciaRegs.SCIFFRX.bit.RXFIFORESET = 1; EDIS; |
I am sending a 16 words from a terminal from my pc, the issue is the reception interrupt don't came. Does something wrong with my C code?
Thank you in advance,
Regards,
S.Tarik