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CCS/TMS320F280049C: How to detect the rising/falling edge of a signal in CLB

jjl3
Intellectual 840 points
Part Number: TMS320F280049C

Tool/software: Code Composer Studio

Dear

I want to detect the rising and falling edge on a GPIO in CLB.

the input of BOUNDARY can support easily,

but the question is the BOUNDARY is only for simulation.

how can I detect the both edges in reality?

thanks!

BR

jjl3

  • 0
    TI__Guru 52040 points

    You can use the INPUT FILTER of the CLB module to detect rising edges. Obviously you can always invert the GPIO signal for falling edge inside the GPIO module.

    Nima

  • 0 in reply to Nima Eskandari
    Intellectual 840 points

    Dear Nima

    thanks for your reply!

    Actually I want the rising edge, falling edge and the current value of one signal,

    so the way of using the input filter is not suitable for me.

    I want to implement this functions like the FPGA, for example,

    using the signal i0 and the signal i0_d(one clock delay) to judge if it is the rising edge or falling edge.

    so I want to produce the signal i0_d, which is one system clock delay, as below:

    but due to the result of simulation, it is not correct.

    How to implement the function?

    the logics inside of CLB is sequenced logics or combined logics?  

    thanks!

    br

    jjl3

  • 0 in reply to jjl3
    TI__Guru 52040 points

    You can use THREE inputs to the CLB tile. Select the same source for all three (your GPIO), for one input, enable the input filter with rising edge detect, for the second input enable the rising edge detect, and for the third do not use the input filter and pass it to the TILE as a RAW input to have the current levels.