TMS320F28377S: SPI slave and RX Fifo buffer

Hi,

Here is the understanding of your problem:-

You're concerned that you might miss your SPI received data (overrun condition) as your application might be busy with other interrupts which may have higher priority over SPI interrupt. Am I correct?

In F28377S (SPI) FIFO depth is 16 level deep x 16 bit. So, you don't need to take SPI receive interrupt each time SPI receives data. You can configure SPI RX FIFO register to trigger receive interrupt after 16 (max limit) SPI word (16-bit) is received. This way you can increase time between SPI receive data ready interrupt.

Another approach is to use DMA instead of CPU to read the SPI received data. This way you can freeing up CPU bandwidth.

Regards,

Manoj

Hello,

Ok, I will try to be less confuse. Let on the side the interrupt priority.

Conseider I'm in SPI Slave. The Cpu receive a 16 bit spi caracter, then I got an Interrupt.

Look at the following screenshot: The master sent one SPI character (0x1503). The we are on the SPI interrupt subroutine.

The RXBUFF is not filled by the received data (0x1503), but stay in SPI_DAT buffer. Then When I get the RXBuffer, I don't get the good data value!

But the RXFFST is weel set to 1 indicating the FIFO has one character...

Hi,

Here is my guess, I'm wondering whether both SPIINT (non-FIFO SPI RX data ready interrupt) and RXFFINT (RX FIFO SPI data ready interrupt) are triggered.

When using SPI RX FIFO, you should be using SPI RX FIFO interrupt (RXFFINT) and not non-FIFO SPI RX interrupt (triggering SPIINT). So, make sure to clear SPIINTENA = 0, this will make sure you aren't getting SPIINT (caused due to non-FIFO SPI RX data ready event)

Regards,

Manoj

You are right,

Initially, I only used the FIFO RX interrupt.

But when I get problem, I read how the Endat stack provided by TI worked (Use SPI in slave also)

Then both are configured!

But with or without the problem is the same.

I think the problem is the slave and master are shifted accordeing its init phase.

I think the master start to transmit during the slave init SPI. So I have a shift of one or many bits into received data.

Then I don't know how syncrhonize both. Ensure the slave is ready to received data before the master send first data....

Once your SPI is configured as slave, it should be ready to receive data from its master. Which device are you using as SPI master?

All you need to do is ensure SPI slave (F28377S) is ready to receive commands from your SPI master. You can have a GPIO from F28377S to tell SPI master that SPI slave configuration is ready.

Regards,

Manoj

It is strange,

I synchronize both Master and slave.

THen all pin state is ok.

But I have always bad data.

When no transmission, I stop both side with debugger. Then on SLave side, I perform a SPI Reset with CCR register from the debugger (just after init phase)

Then next byte receive is Ok.

Now, If I add C code line to perform this reset (set to 0 and then Set to 1) next byte is alays shiffted....