TMS320F28379S: CMPSS offset

Hi,

we're using the TMS320F28379S for motor control application.

we have current sensors in-phase with the motor windings.

we've configured the CMPSS and the ADC to sample the channel.

on the CCS window we can see that the samples on ADCRESULT are stable around mid-point, i.e. 2040-2050.

We're trying to set the CMPSS to trip both at high and low compare values and set the TZ for the PWMs.

we've setup DACLVALS=1900 and DACHVALS=2100.

However the low compare triggers the TZ.

we found that we need to go down to around 1800 so the low comp will not trigger.

with the hi compare with can go down to around 1900 WITHOUT getting any trigger.

it seems like there's some offset of about 200 points on the compare input.

Any idea where that can come from?

on the ADC we're not using any PPB to offset the measurements.

Thanks!!

here's the CMPSS init :

EALLOW;
    //Enable CMPSS
    v->COMPCTL.bit.COMPDACE = 1;
    //NEG signal comes from DAC for the low comparator
    v->COMPCTL.bit.COMPLSOURCE = NEGIN_DAC;
    //NEG signal comes from DAC for the high comparator
    v->COMPCTL.bit.COMPHSOURCE = NEGIN_DAC;
    //Use VDDA as the reference for comparator DACs
    v->COMPDACCTL.bit.SELREF = REFERENCE_VDDA;
    //Set DAC to H~75% and L ~25% values
    v->DACHVALS.bit.DACVAL = Hi;
    v->DACLVALS.bit.DACVAL = Lo;
    // comparator oputput is "not" inverted for high compare event
    v->COMPCTL.bit.COMPHINV = 0;
    // Comparator output is inverted for for low compare event
    v->COMPCTL.bit.COMPLINV = 1;

    // Configure Digital Filter - High
    //Maximum CLKPRESCALE value provides the most time between samples
    v->CTRIPHFILCLKCTL.bit.CLKPRESCALE = clkPrescale;  //30;   /* Max count of 1023 */
    //Maximum SAMPWIN value provides largest number of samples
    v->CTRIPHFILCTL.bit.SAMPWIN        = sampwin;  //0x1F;
    //Maximum THRESH value requires static value for entire window
    //  THRESH should be GREATER than half of SAMPWIN
    v->CTRIPHFILCTL.bit.THRESH         = thresh;  //0x1F;
    //Reset filter logic & start filtering
    v->CTRIPHFILCTL.bit.FILINIT        = 1;


    // Configure Digital Filter - Low
    //Maximum CLKPRESCALE value provides the most time between samples
    v->CTRIPLFILCLKCTL.bit.CLKPRESCALE = clkPrescale;  //30;   /* Max count of 1023 */
    //Maximum SAMPWIN value provides largest number of samples
    v->CTRIPLFILCTL.bit.SAMPWIN        = sampwin;  //0x1F;
    //Maximum THRESH value requires static value for entire window
    //  THRESH should be GREATER than half of SAMPWIN
    v->CTRIPLFILCTL.bit.THRESH         = thresh;  //0x1F;
    //Reset filter logic & start filtering
    v->CTRIPLFILCTL.bit.FILINIT        = 1;

    // Configure CTRIPOUT path

    //Digital filter HIGH output feeds CTRIPH and CTRIPOUTH
    v->COMPCTL.bit.CTRIPHSEL           = CTRIP_FILTER;
    v->COMPCTL.bit.CTRIPOUTHSEL        = CTRIP_FILTER;

    //Digital filter LOW output feeds CTRIPH and CTRIPOUTH
    v->COMPCTL.bit.CTRIPLSEL           = CTRIP_FILTER;
    v->COMPCTL.bit.CTRIPOUTLSEL        = CTRIP_FILTER;

    // Make sure the asynchronous path compare high and low event
    // does not go to the OR gate with latched digital filter output
    v->COMPCTL.bit.ASYNCHEN = 0;
    v->COMPCTL.bit.ASYNCLEN = 0;

    //Comparator hysteresis control , set to 2x typical value
    v->COMPHYSCTL.bit.COMPHYS = 4;
    // Dac value is updated on sysclock
    v->COMPDACCTL.bit.SWLOADSEL = 0;
    // ramp is bypassed
    v->COMPDACCTL.bit.DACSOURCE = 0;
    // Clear the latched comparator events
    v->COMPSTSCLR.bit.HLATCHCLR = 1;
    v->COMPSTSCLR.bit.LLATCHCLR = 1;

    EDIS;