Tool/software: Code Composer Studio
Hi everyone,
I have a project running from Flash but I want to run from RAM the funtions in IQmath.lib and also the main interruption. Something similar to the procedure followed in the example project SolarMicroInv_F2803x but with the TMS320F28027F. The main interrupt is driven by the ADC which is trigger by the PWM, I can see in debug that the ADC result is running (values change when I apply different voltages to the ADC pins), so the interruption is triggered, however the interruption routine is not executed. Same problem with IQmath functions. Is there any document for reference?
In the main file (declaration area) I use the next #pragma for the RAM interruptions routines:
#ifdef FLASH #pragma CODE_SECTION(Inv_ISR,"ramfuncs"); #pragma CODE_SECTION(OneKhzISR,"ramfuncs"); #endif //This is the control loop ISR run at 50Khz interrupt void Inv_ISR(void); //This is 1 Khz ISR slaved off CPU timer 2, interrupt void OneKhzISR(); later in the main function:
#ifdef FLASH // Copy time critical code and Flash setup code to RAM // The RamfuncsLoadStart, RamfuncsLoadEnd, and RamfuncsRunStart // symbols are created by the linker. Refer to the linker files. MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); MemCopy(&IQfuncsLoadStart, &IQfuncsLoadEnd, &IQfuncsRunStart); // Call Flash Initialization to setup flash waitstates // This function must reside in RAM InitFlash(); // Call the flash wrapper init function #endif //(FLASH)
Also the Interrupts and ISR initialization:
EALLOW; PieVectTable.ADCINT1 = &Inv_ISR; // Inverter Control Interrupt PieVectTable.TINT2 = &OneKhzISR; // 1kHz interrupt from CPU timer 2 PieCtrlRegs.PIEIER1.bit.INTx1 = 1; // Enable ADCINT1 in PIE group 1 //ADC interrupt already enabled by ADC SOC Cnf IER |= M_INT1; // Enable CPU INT1 for ADCINT1,ADCINT2,ADCINT9,TripZone IER |= M_INT14; // CPU timer 2 is connected to CPU INT 14 EINT; // Enable Global interrupt INTM ERTM; // Enable Global realtime interrupt DBGM EDIS;
This is the interruption routine that is not executed:
interrupt void Inv_ISR() {
GpioDataRegs.GPATOGGLE.bit.GPIO12;
interrupt void Inv_ISR() {
//GpioDataRegs.GPATOGGLE.bit.GPIO12; //Debugging
GpioDataRegs.GPASET.bit.GPIO12 = 0;
//-------------------------------------------------------------------
// Acknowledge interrupt
//-------------------------------------------------------------------
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1; // Must acknowledge the PIE group
AdcRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Clear ADCINT1 flag
//-------------------------------------------------------------------
return;
}
Following the custom FLASH.cmd
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F28027_FLASH_BlinkingLED.CMD */
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F28027 */
/* */
/* Version: 1.1 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments © 2009 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 04/24/09 | Release 1.1 */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F28022
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2802x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0:
/* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
progRAM : origin = 0x008000, length = 0x000800
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHD : origin = 0x3F0000, length = 0x002000 /* on-chip FLASH */
FLASHC : origin = 0x3F2000, length = 0x002000 /* on-chip FLASH */
FLASHA : origin = 0x3F6000, length = 0x001F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
IQTABLES : origin = 0x3FE000, length = 0x000B50 /* IQ Math Table in Boot */
IQTABLES2 : origin = 0x3FEB50, length = 0x00008C /* IQ Math Table in Boot */
IQTABLES3 : origin = 0x3FEBDC, length = 0x0000AA /* IQ Math Table in Boot */
BOOTROM : origin = 0x3FF27C, length = 0x000D44 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000050, length = 0x0003B0
RAMM1 : origin = 0x000400, length = 0x000400
dataRAM : origin = 0x008800, length = 0x000800
FLASHB : origin = 0x3F4000, length = 0x002000
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHD,
RUN = progRAM,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.esysmem : > dataRAM, PAGE = 1
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
//IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmath : LOAD = FLASHA,
RUN = progRAM,
LOAD_START(_IQfuncsLoadStart),
LOAD_END(_IQfuncsLoadEnd),
RUN_START(_IQfuncsRunStart),
PAGE = 0
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
cntl_coeff_RAM : > dataRAM, PAGE=1
cntl_var_RAM : > RAMM1, PAGE =1
}
SECTIONS
{
/************* DPLIB Sections C28x ************************/
/* ADCDRV_1ch section */
ADCDRV_1ch_Section : > dataRAM PAGE = 1
/* ADCDRV_4ch section */
ADCDRV_4ch_Section : > dataRAM PAGE = 1
/* CNTL_2P2Z section */
CNTL_2P2Z_Section : > dataRAM PAGE = 1
CNTL_2P2Z_InternalData : > dataRAM PAGE = 1
CNTL_2P2Z_Coef : > dataRAM PAGE = 1
/* CNTL_3P3Z section */
CNTL_3P3Z_Section : > dataRAM PAGE = 1
CNTL_3P3Z_InternalData : > dataRAM PAGE = 1
CNTL_3P3Z_Coef : > dataRAM PAGE = 1
/*DLOG_4CH section */
DLOG_4CH_Section : > dataRAM PAGE = 1
DLOG_BUFF : > dataRAM PAGE = 1
/*MATH_EMAVG section */
MATH_EMAVG_Section : > dataRAM PAGE = 1
/*PFC_ICMD section*/
PFC_ICMD_Section : > dataRAM PAGE = 1
/*PFC_INVSQR section*/
PFC_INVSQR_Section : > dataRAM PAGE = 1
/* PWMDRV_1ch driver section */
PWMDRV_1ch_Section : > dataRAM PAGE = 1
/* PWMDRV_1chHiRes driver section */
PWMDRV_1chHiRes_Section : > dataRAM PAGE = 1
/* PWMDRV_PFC2PhiL driver section */
PWMDRV_PFC2PhiL_Section : > dataRAM PAGE = 1
/* PWMDRV_PSFB driver section */
PWMDRV_PSFB_Section : > dataRAM PAGE = 1
/* PWMDRV_DualUpDwnCnt driver section */
PWMDRV_DualUpDwnCnt_Section : > dataRAM PAGE = 1
/* PWMDRV_ComplPairDB driver section */
PWMDRV_ComplPairDB_Section : > dataRAM PAGE = 1
/* ZeroNet_Section */
ZeroNet_Section : > dataRAM PAGE = 1
}
