• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 82 subscribers
  • Views 522 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28379D: Timing of the SDFM module

Ralf Bartling
Expert 1225 points

Part Number: TMS320F28379D

Hello,
I have a question regarding the timing of the SDFM module.

In my application the SDFM module works with 10MHz SD-C clock. The SDFM module is synchronized to the zero event of the EPWM unit. This works fine.

Now I have found out, that there is delay between the zero event of the EPWM unit and the setting of the AF-Bit in the SDFM module which indicates new data available from the SDFM module. I have measured a delay between 520ns and 560ns.

Is this delay systematic?

I want to write a routine in order to check the synchronism between EPWM and SDFM during runtime, because a resynchronize of the SDFM module yields in wrong results for the first three cycles (with sinc3 filter).  

Is it possible to rely on the delay time?


Best regards
Ralf

  • 0
    TI__Guru 55700 points

    Ralf,

    On a SDSYNC event (from PWM to SDFM), filter channel needs atleast latency of Sinc filter + 5 SD-Cx cycles to settle down and read correct filter results.

    For example: In a Sinc3 filter, on a SDSYNC event, first 2 samples of filter after SDSYNC event will be incorrect, this is due to the nature of SDFM filter architecture. There is no way to get around the first 2 incorect samples of filter. If you which avoid reading these incorrect samples, just ignore these first 2 samples after SDSYNC event.

    Latency of Sinc filter = Order of Sinc filter x SD-Cx period x DOSR, additional 5-SD-Cx cycles is provided to ensure the filter results are correctly latched to memory mapped register. Below thread also discusses the same topic.

    Is this delay systematic?

    Yes, it is deterministic as shown in above formulae.

    Regards,

    Manoj