According to spruhm8i, each CLB input contains a selectable synchronizer. Other than the mention of its existance and the register to select it, I have been unable to find anything which explains the function of this block. So a few questions:
- Is there any documentation which describes the synchronizer and the delays associated with its use?
- Can I assume that the synchronizer uses the same clock as the CLB tiles?
- Can I also I assume that the delay from the output of the synchronizer is such that its output can be clocked within the tile, even after going through a lot of combinatorial logic?
- Due to setup and hold considerations, could it ever miss a one clock pulse such as a PWM CTR=x signal (see Table 26-1)?
- Due to setup and hold considerations, could it ever miss a one clock pulse which entered the input via AUXSIGx from another tile (see Table 26-1)?