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TMS320F28035: Testing for illegal opcode

Wayne Huang
Genius 16685 points
Part Number: TMS320F28035
Other Parts Discussed in Thread: C2000WARE

Dear Champs,

I am asking this for our customer.

Do we have any doc or example code to show testing for illegal opcode (ITRAP) and illegal ISR?

Wayne Huang

  • 0
    TI__Genius 10845 points

    Hi,
    This query has been assigned to the experts. Due to the US Holiday on 25/05, please expect reply by 26/05 US time.

    Thanks
    Vasudha

  • 0 in reply to Vasudha Bhadoria
    TI__Guru 50611 points

    Hi,

    There is an example in C2000ware which illustrates the ITRAP and illegal ISR.

    It is at 

    C:\C2000Ware_3_01_00_00\device_supportf\2803x\examples/c28\sw_prioritized_interrupts\Example_2803xSWPrioritizedDefaultIsr.c

  • 0 in reply to Santosh Jha
    TI__Genius 16685 points

    Dear Santosh,

    Do you mean this?

    //
    // ILLEGAL_ISR - Illegal operation TRAP is connected to ITRAP of CPU
    // (non-maskable)
    //
    __interrupt void
    ILLEGAL_ISR(void)
    {
    EINT;

    //
    // Insert ISR Code here
    //

    //
    // Next two lines for debug only to halt the processor here
    // Remove after inserting ISR Code
    //
    __asm (" ESTOP0");
    for(;;);
    }

    However, how does the user generate or trigger an ITRAP event so that this ISR can be served?

    Wayne Huang

  • 0 in reply to Wayne Huang
    TI__Genius 17315 points

    Wayne,

    From the TRM:

    "If an illegal opcode is fetched, the device will take an ITRAP (illegal trap) interrupt. During the boot process, the interrupt vector used by the ITRAP is within the CPU vector table of the boot ROM. The ITRAP vector points to an interrupt service routine (ISR) within the boot ROM named ITRAPIsr(). This interrupt service routine attempts to enable the watchdog and then loops forever until the processor is reset. This ISR will be used for any ITRAP until the user's application initializes and enables the peripheral interrupt expansion (PIE) block. Once the PIE is enabled, the ITRAP vector located within the PIE vector table will be used."

    Specifically, if I understand your question, the customer wants to generate (or force) a trigger for testing their ITRAP ISR after the application has been initialized.  One possible way to force an ILLEGAL_ISR is to use the inline assembly instruction TRAP #19.  Please see the TMS320C28x CPU and Instruction Set Reference Guide, page 440:

    http://www.ti.com/lit/spru430

    This will generate a 'software' ILLEGAL trap.  However, this probably runs ITRAPIsr() in the boot ROM and not from the PIE (need to test).  As for the PIE block, the ILLEGAL_ISR vector is located at 0x000D26 (see the F2803x workshop code PieVect_5_6_7_8_9_10.c file - this includes the address in the comments where the bit-field examples do not).  Once a PIE interrupt is generated, the address appears in the PIEVECT field of the PIECTRL register.  It would be convenient to be able to write "0x000D26" to this field, however this field is read-only.  Please see the F2803x TRM on page 163:

    http://www.ti.com/lit/sprui10

    Here you will find an example for an illegal operation.  The only other way I can think of is to have the customer create an illegal operation/instruction and run it.  I am not sure if this helps, but I wanted to share this with you.

    - Ken

  • 0 in reply to Ken Schachter
    TI__Guru 50611 points

    Wayne,

    Any update on the issue? Has it been resolved?