how to configure ecan to communicate between two dsp(tms320f28035)

shuyoe chen

Other Parts Discussed in Thread: SN65HVD230

#include "DSP2803x_Device.h"     // DSP28 Headerfile Include File
#include "DSP2803x_Examples.h"   // DSP28 Examples Include File


void initmaster(void)        // Initialize eCAN-A module
{
struct ECAN_REGS ECanaShadow;
   EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
///    EDIS;


/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. */


///    EALLOW;     // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
                                    // HECC mode also enables time-stamping feature
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//  as a matter of precaution.

    ECanaRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */

    ECanaRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;
    /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */

    ECanaShadow.CANBTC.bit.BRPREG = 2;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;

    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs
///    EDIS;

    ECanaMboxes.MBOX0.MSGID.all = 0x80000000;//0x9555AAA0;
    ECanaMboxes.MBOX1.MSGID.all = 0x80000001;//0x9555AAA1;
    ECanaMboxes.MBOX2.MSGID.all = 0x80000002;//0x9555AAA2;
    ECanaMboxes.MBOX3.MSGID.all = 0x80000003;//0x9555AAA3;
    ECanaMboxes.MBOX4.MSGID.all = 0x80000004;//0x9555AAA4;
    ECanaMboxes.MBOX5.MSGID.all = 0x80000005;//0x9555AAA5;
    ECanaMboxes.MBOX6.MSGID.all = 0x80000006;//0x9555AAA6;
    ECanaMboxes.MBOX7.MSGID.all = 0x80000007;//0x9555AAA7;
    ECanaMboxes.MBOX8.MSGID.all = 0x80000008;//0x9555AAA8;
    ECanaMboxes.MBOX9.MSGID.all = 0x80000009;//0x9555AAA9;
    ECanaMboxes.MBOX10.MSGID.all = 0x8000000a;//0x9555AAAA;
    ECanaMboxes.MBOX11.MSGID.all = 0x8000000b;//0x9555AAAB;
    ECanaMboxes.MBOX12.MSGID.all = 0x8000000c;//0x9555AAAC;
    ECanaMboxes.MBOX13.MSGID.all = 0x8000000d;//0x9555AAAD;
    ECanaMboxes.MBOX14.MSGID.all = 0x8000000e;//0x9555AAAE;
    ECanaMboxes.MBOX15.MSGID.all = 0x8000000f;//0x9555AAAF;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x81111110;//0x9555AAA0;
    ECanaMboxes.MBOX17.MSGID.all = 0x81111111;//0x9555AAA1;
    ECanaMboxes.MBOX18.MSGID.all = 0x81111112;//0x9555AAA2;
    ECanaMboxes.MBOX19.MSGID.all = 0x81111113;//0x9555AAA3;
    ECanaMboxes.MBOX20.MSGID.all = 0x81111114;//0x9555AAA4;
    ECanaMboxes.MBOX21.MSGID.all = 0x81111115;//0x9555AAA5;
    ECanaMboxes.MBOX22.MSGID.all = 0x81111116;//0x9555AAA6;
    ECanaMboxes.MBOX23.MSGID.all = 0x81111117;//0x9555AAA7;
    ECanaMboxes.MBOX24.MSGID.all = 0x81111118;//0x9555AAA8;
    ECanaMboxes.MBOX25.MSGID.all = 0x81111119;//0x9555AAA9;
    ECanaMboxes.MBOX26.MSGID.all = 0x8111111a;//0x9555AAAA;
    ECanaMboxes.MBOX27.MSGID.all = 0x8111111b;//0x9555AAAB;
    ECanaMboxes.MBOX28.MSGID.all = 0x8111111c;//0x9555AAAC;
    ECanaMboxes.MBOX29.MSGID.all = 0x8111111d;//0x9555AAAD;
    ECanaMboxes.MBOX30.MSGID.all = 0x8111111e;//0x9555AAAE;
    ECanaMboxes.MBOX31.MSGID.all = 0x8111111f;//0x9555AAAF;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0xFFFF0000;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 4;//8;

    // Write to the mailbox RAM field of MBOX0 - 15
    ECanaMboxes.MBOX0.MDL.all = 0x12345678;
    ECanaMboxes.MBOX0.MDH.all = 0x13579ace;

    ECanaMboxes.MBOX1.MDL.all = 0x11111111;
    ECanaMboxes.MBOX1.MDH.all = 0x11111111;

    ECanaMboxes.MBOX2.MDL.all = 0x22222222;
    ECanaMboxes.MBOX2.MDH.all = 0x22222222;

    ECanaMboxes.MBOX3.MDL.all = 0x33333333;
    ECanaMboxes.MBOX3.MDH.all = 0x33333333;

    ECanaMboxes.MBOX4.MDL.all = 0x44444444;
    ECanaMboxes.MBOX4.MDH.all = 0x44444444;

    ECanaMboxes.MBOX5.MDL.all = 0x55555555;
    ECanaMboxes.MBOX5.MDH.all = 0x55555555;

    ECanaMboxes.MBOX6.MDL.all = 0x66666666;
    ECanaMboxes.MBOX6.MDH.all = 0x66666666;

    ECanaMboxes.MBOX7.MDL.all = 0x77777777;
    ECanaMboxes.MBOX7.MDH.all = 0x77777777;

    ECanaMboxes.MBOX8.MDL.all = 0x88888888;
    ECanaMboxes.MBOX8.MDH.all = 0x88888888;

    ECanaMboxes.MBOX9.MDL.all = 0x99999999;
    ECanaMboxes.MBOX9.MDH.all = 0x99999999;

    ECanaMboxes.MBOX10.MDL.all = 0xaaaaaaaa;
    ECanaMboxes.MBOX10.MDH.all = 0xaaaaaaaa;

    ECanaMboxes.MBOX11.MDL.all = 0xbbbbbbbb;
    ECanaMboxes.MBOX11.MDH.all = 0xbbbbbbbb;

    ECanaMboxes.MBOX12.MDL.all = 0xcccccccc;
    ECanaMboxes.MBOX12.MDH.all = 0xcccccccc;

    ECanaMboxes.MBOX13.MDL.all = 0xdddddddd;
    ECanaMboxes.MBOX13.MDH.all = 0xdddddddd;

    ECanaMboxes.MBOX14.MDL.all = 0xeeeeeeee;
    ECanaMboxes.MBOX14.MDH.all = 0xeeeeeeee;

    ECanaMboxes.MBOX15.MDL.all = 0xffffffff;
    ECanaMboxes.MBOX15.MDH.all = 0xffffffff;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
///    EALLOW;
///    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
///    EALLOW;
///    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
///    ECanaShadow.CANMC.bit.STM = 1;    // Configure CAN for self-test mode
///    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
///    EDIS;


}

Fullscreen 0508.canmaster.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

void main(void)
{
//   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();
   DINT;
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();
	setcanm(); // Initialize eCAN-A module

    for(;;)
    {
       ECanaRegs.CANTRS.all = 0x0000FFFF;  // Set TRS for all transmit mailboxes
       while(ECanaRegs.CANTA.all != 0x0000FFFF ) {}  // Wait for all TAn bits to be set..
       ECanaRegs.CANTA.all = 0x0000FFFF;   // Clear all TAn

    }
}

Fullscreen 7455.initslave.txt Download

#include "DSP2803x_Device.h"     // DSP28 Headerfile Include File
#include "DSP2803x_Examples.h"   // DSP28 Examples Include File


void initslave(void)        // Initialize eCAN-A module
{
struct ECAN_REGS ECanaShadow;
   EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
///    EDIS;


/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. */


///    EALLOW;     // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

/* Configure eCAN for HECC mode - (reqd to access mailboxes 16 thru 31) */
                                    // HECC mode also enables time-stamping feature
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//  as a matter of precaution.

    ECanaRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */

    ECanaRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */

    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;
    /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */

    ECanaShadow.CANBTC.bit.BRPREG = 2;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;

    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs
///    EDIS;

    ECanaMboxes.MBOX0.MSGID.all = 0x80000000;//0x9555AAA0;
    ECanaMboxes.MBOX1.MSGID.all = 0x80000001;//0x9555AAA1;
    ECanaMboxes.MBOX2.MSGID.all = 0x80000002;//0x9555AAA2;
    ECanaMboxes.MBOX3.MSGID.all = 0x80000003;//0x9555AAA3;
    ECanaMboxes.MBOX4.MSGID.all = 0x80000004;//0x9555AAA4;
    ECanaMboxes.MBOX5.MSGID.all = 0x80000005;//0x9555AAA5;
    ECanaMboxes.MBOX6.MSGID.all = 0x80000006;//0x9555AAA6;
    ECanaMboxes.MBOX7.MSGID.all = 0x80000007;//0x9555AAA7;
    ECanaMboxes.MBOX8.MSGID.all = 0x80000008;//0x9555AAA8;
    ECanaMboxes.MBOX9.MSGID.all = 0x80000009;//0x9555AAA9;
    ECanaMboxes.MBOX10.MSGID.all = 0x8000000a;//0x9555AAAA;
    ECanaMboxes.MBOX11.MSGID.all = 0x8000000b;//0x9555AAAB;
    ECanaMboxes.MBOX12.MSGID.all = 0x8000000c;//0x9555AAAC;
    ECanaMboxes.MBOX13.MSGID.all = 0x8000000d;//0x9555AAAD;
    ECanaMboxes.MBOX14.MSGID.all = 0x8000000e;//0x9555AAAE;
    ECanaMboxes.MBOX15.MSGID.all = 0x8000000f;//0x9555AAAF;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x81111110;//0x9555AAA0;
    ECanaMboxes.MBOX17.MSGID.all = 0x81111111;//0x9555AAA1;
    ECanaMboxes.MBOX18.MSGID.all = 0x81111112;//0x9555AAA2;
    ECanaMboxes.MBOX19.MSGID.all = 0x81111113;//0x9555AAA3;
    ECanaMboxes.MBOX20.MSGID.all = 0x81111114;//0x9555AAA4;
    ECanaMboxes.MBOX21.MSGID.all = 0x81111115;//0x9555AAA5;
    ECanaMboxes.MBOX22.MSGID.all = 0x81111116;//0x9555AAA6;
    ECanaMboxes.MBOX23.MSGID.all = 0x81111117;//0x9555AAA7;
    ECanaMboxes.MBOX24.MSGID.all = 0x81111118;//0x9555AAA8;
    ECanaMboxes.MBOX25.MSGID.all = 0x81111119;//0x9555AAA9;
    ECanaMboxes.MBOX26.MSGID.all = 0x8111111a;//0x9555AAAA;
    ECanaMboxes.MBOX27.MSGID.all = 0x8111111b;//0x9555AAAB;
    ECanaMboxes.MBOX28.MSGID.all = 0x8111111c;//0x9555AAAC;
    ECanaMboxes.MBOX29.MSGID.all = 0x8111111d;//0x9555AAAD;
    ECanaMboxes.MBOX30.MSGID.all = 0x8111111e;//0x9555AAAE;
    ECanaMboxes.MBOX31.MSGID.all = 0x8111111f;//0x9555AAAF;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0x0000FFFF;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 4;//8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 4;//8;

}

Fullscreen 5327.canslave.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
void mailbox_chec(int32 T1, int32 T2, int32 T3);
void mailbox_rea(int16 i);

// Global variable for this example
Uint32  ErrorCoun;
Uint32  PassCoun;
Uint32  MessageReceivedCoun;

Uint32  TestMbo1 = 0;
Uint32  TestMbo2 = 0;
Uint32  TestMbo3 = 0; 

void main(void)
{
    Uint16  j;
//   struct ECAN_REGS ECanaShadow;

   InitSysCtrl();
   DINT;
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();
    MessageReceivedCoun = 0;
    ErrorCoun = 0;
    PassCoun = 0; 
	setcans(); // Initialize eCAN-A module

    for(;;)
    {
       //Read from Receive mailboxes and begin checking for data */
       for(j=0; j<16; j++)         // Read & check 16 mailboxes
       {
          mailbox_rea(j);         // This func reads the indicated mailbox data
          mailbox_chec(TestMbo1,TestMbo2,TestMbo3); // Checks the received data
       }
    }
}

// This function reads out the contents of the indicated
// by the Mailbox number (MBXnbr).
void mailbox_rea(int16 MBXnb)
{
   volatile struct MBOX *Mailbo;
   Mailbo = &ECanaMboxes.MBOX0 + MBXnb;
   TestMbo1 = Mailbo->MDL.all; // = 0x9555AAAn (n is the MBX number)
   TestMbo2 = Mailbo->MDH.all; // = 0x89ABCDEF (a constant)
   TestMbo3 = Mailbo->MSGID.all;// = 0x9555AAAn (n is the MBX number)

} // MSGID of a rcv MBX is transmitted as the MDL data.

void mailbox_chec(int32 T1, int32 T2, int32 T3)
{
    if((T1 != T3) || ( T2 != 0x89ABCDEF))
    {
       ErrorCoun++;
    }
    else
    {
       PassCoun++;
    }
}

i have compose four files for initial and main in both side.

then i used 2 computer and 2 ICE(development board) connecting throught a IC (SN65HVD230). but i don't know why it didn't work.

can any one please help to correct my code? cuz i can't find out any wrong in it.

please.

those Filename Extensions should be exchanged into .c (not .txt)

over 15 years ago

0 Frank Bormann over 15 years ago

Mastermind 7585 points

Your receiver part in your slave is wrong, the for-loop without any handshake doesn't make sense. Before you actually can read a message, you have to wait until a RMP bit has been set by the CAN controller. Only then you can read the corresponding mailbox, followed by a reset of the RMP bit. This is the simplest solution but of course an interrupt driven approach would be much smarter.

0 shuyoe chen over 15 years ago in reply to Frank Bormann

Prodigy 90 points

thanks your reply

yes, you are right, i did before. i know what you mean. would you please see those files below?

yeah~~ i have the same idea using interrupt to recieve those data. but i think i should know how to configure

ecan in base then adding more function.

i correct many times. following one is one of it.

please~~~

Fullscreen 3301.initial_both.txt Download

#include "DSP2803x_Device.h"     // DSP28 Headerfile Include File
#include "DSP2803x_Examples.h"   // DSP28 Examples Include File


void setcan(void)        // Initialize eCAN-A module
{
struct ECAN_REGS ECanaShadow;
   EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
    EDIS;


/* Create a shadow register structure for the CAN control registers. This is
 needed, since only 32-bit access is allowed to these registers. 16-bit access
 to these registers could potentially corrupt the register contents or return
 false data. */


    EALLOW;     // EALLOW enables access to protected bits

/* Configure eCAN RX and TX pins for CAN operation using eCAN regs*/
    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

	    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

/* Initialize all bits of 'Message Control Register' to zero */
// Some bits of MSGCTRL register come up in an unknown state. For proper operation,
// all bits (including reserved bits) of MSGCTRL must be initialized to zero
    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

    ECanaRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */
    ECanaRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..

    ECanaShadow.CANBTC.all = 0;
    /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */
    ECanaShadow.CANBTC.bit.BRPREG = 2;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;
    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs


}

Fullscreen 2627.receive_slave.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

long i,rxcount=0;

void setcan(void);
 
void main(void)
{
//   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();
   DINT;
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();

   setcan();

   ECanaMboxes.MBOX0.MSGID.all = 0x80000000;
   ECanaRegs.CANMD.all = 0x00000001;
   ECanaRegs.CANME.all = 0xFFFFFFFF;
   ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8; 
   while(1)
   {
    while(ECanaRegs.CANRMP.all!=0x00000001){}
    ECanaRegs.CANRMP.all=0x00000001;
    rxcount++;
   }

}

Fullscreen 7536.send_master.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
#define txcount 10000
long i,loopcount=0;

void setcan(void);
 
void main(void)
{
   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();
   DINT;
   InitPieCtrl();
   IER = 0x0000;
   IFR = 0x0000;
   InitPieVectTable();

   setcan();

   ECanaMboxes.MBOX0.MSGID.all = 0x80000000;
   ECanaRegs.CANMD.all = 0x00000000;
   ECanaRegs.CANME.all = 0x00000001;
   ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;

   ECanaMboxes.MBOX0.MDL.all = 0x12345678;
   ECanaMboxes.MBOX0.MDH.all = 0x13579ace;

   for(i=0;i<txcount;i++)
   {
       ECanaRegs.CANTRS.all = 0x00000000;  // Set TRS for all transmit mailboxes
       ECanaRegs.CANTRS.all = 0x00000001;
       while(ECanaRegs.CANTA.all != 0x00000001 ) {}  // Wait for all TAn bits to be set..

       ECanaRegs.CANTA.all = 0x00000000;   // Clear all TAn
       ECanaRegs.CANTA.all = 0x00000001; 
       loopcount++;
   }

}

thanks a million

0 Frank Bormann over 15 years ago in reply to shuyoe chen

Mastermind 7585 points

Again, your slave receiver code is wrong.

(1) It is no good to initialize just DLC and leave the remaining bits in MSGCTRL at random, that's basic C stuff.

Recommendation:

ECanaMboxes.MBOX0.MSGCTRL.all = 0;

ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;

(2) The wait construction for mailbox 0 is wrong:

while(ECanaRegs.CANRMP.all!=0x00000001){}
ECanaRegs.CANRMP.all=0x00000001;

Recommendation:

while((ECanaRegs.CANRMP.all & 1) !=1) {}
ECanaRegs.CANRMP.all= 1;

0 shuyoe chen over 15 years ago in reply to Frank Bormann

Prodigy 90 points

yes, you are right. those things i have tried before. would you please correct me again?

i am a new programmer without any experience of program.

and my first touch of program is for this dsp. teach me please !

those 3 were done every things you said before, and did not work .

Fullscreen 8255.slave11.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File

long i=0;
void main(void)
{

   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();

    EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
    EDIS;
 
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
	initboth11(); // Initialize eCAN-A module

    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
    ECanaMboxes.MBOX0.MSGID.all = 0x81111110;
    ECanaMboxes.MBOX1.MSGID.all = 0x81111111;
    ECanaMboxes.MBOX2.MSGID.all = 0x81111112;
    ECanaMboxes.MBOX3.MSGID.all = 0x81111113;
    ECanaMboxes.MBOX4.MSGID.all = 0x81111114;
    ECanaMboxes.MBOX5.MSGID.all = 0x81111115;
    ECanaMboxes.MBOX6.MSGID.all = 0x81111116;
    ECanaMboxes.MBOX7.MSGID.all = 0x81111117;
    ECanaMboxes.MBOX8.MSGID.all = 0x81111118;
    ECanaMboxes.MBOX9.MSGID.all = 0x81111119;
    ECanaMboxes.MBOX10.MSGID.all = 0x8111111A;
    ECanaMboxes.MBOX11.MSGID.all = 0x8111111B;
    ECanaMboxes.MBOX12.MSGID.all = 0x8111111C;
    ECanaMboxes.MBOX13.MSGID.all = 0x8111111D;
    ECanaMboxes.MBOX14.MSGID.all = 0x8111111E;
    ECanaMboxes.MBOX15.MSGID.all = 0x8111111F;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x80000000;
    ECanaMboxes.MBOX17.MSGID.all = 0x80000001;
    ECanaMboxes.MBOX18.MSGID.all = 0x80000002;
    ECanaMboxes.MBOX19.MSGID.all = 0x80000003;
    ECanaMboxes.MBOX20.MSGID.all = 0x80000004;
    ECanaMboxes.MBOX21.MSGID.all = 0x80000005;
    ECanaMboxes.MBOX22.MSGID.all = 0x80000006;
    ECanaMboxes.MBOX23.MSGID.all = 0x80000007;
    ECanaMboxes.MBOX24.MSGID.all = 0x80000008;
    ECanaMboxes.MBOX25.MSGID.all = 0x80000009;
    ECanaMboxes.MBOX26.MSGID.all = 0x8000000A;
    ECanaMboxes.MBOX27.MSGID.all = 0x8000000B;
    ECanaMboxes.MBOX28.MSGID.all = 0x8000000C;
    ECanaMboxes.MBOX29.MSGID.all = 0x8000000D;
    ECanaMboxes.MBOX30.MSGID.all = 0x8000000E;
    ECanaMboxes.MBOX31.MSGID.all = 0x8000000F;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0xFFFF0000;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
///    EALLOW;
///    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
///    EALLOW;
///    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
///    ECanaShadow.CANMC.bit.STM = 1;    // Configure CAN for self-test mode
///    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
///    EDIS;

    // Begin waitttttttinggggggggggggg
    for(;;)
    {
       while(ECanaRegs.CANRMP.all != 0x0000FFFF ) {}  // Wait for all RMPn bits to be set..
       ECanaRegs.CANRMP.all = 0x0000FFFF;   // Clear all RMPn
       i++;
    }
}

Fullscreen 3036.master11.txt Download

#include "DSP28x_Project.h"     // Device Headerfile and Examples Include File
void initboth11(void);
void main(void)
{

   struct ECAN_REGS ECanaShadow;
   InitSysCtrl();

    EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO30 = 0;     // Enable pull-up for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAPUD.bit.GPIO31 = 0;     // Enable pull-up for GPIO31 (CANTXA)
    GpioCtrlRegs.GPAQSEL2.bit.GPIO30 = 3;   // Asynch qual for GPIO30 (CANRXA)
    GpioCtrlRegs.GPAMUX2.bit.GPIO30 = 1;    // Configure GPIO30 for CANRXA operation
    GpioCtrlRegs.GPAMUX2.bit.GPIO31 = 1;    // Configure GPIO31 for CANTXA operation
//    EDIS;
 
    DINT;
    InitPieCtrl();
    IER = 0x0000;
    IFR = 0x0000;
    InitPieVectTable();
	initboth11(); // Initialize eCAN-A module
    EALLOW;
    // Mailboxs can be written to 16-bits or 32-bits at a time
    // Write to the MSGID field of TRANSMIT mailboxes MBOX0 - 15
    ECanaMboxes.MBOX0.MSGID.all = 0x80000000;
    ECanaMboxes.MBOX1.MSGID.all = 0x80000001;
    ECanaMboxes.MBOX2.MSGID.all = 0x80000002;
    ECanaMboxes.MBOX3.MSGID.all = 0x80000003;
    ECanaMboxes.MBOX4.MSGID.all = 0x80000004;
    ECanaMboxes.MBOX5.MSGID.all = 0x80000005;
    ECanaMboxes.MBOX6.MSGID.all = 0x80000006;
    ECanaMboxes.MBOX7.MSGID.all = 0x80000007;
    ECanaMboxes.MBOX8.MSGID.all = 0x80000008;
    ECanaMboxes.MBOX9.MSGID.all = 0x80000009;
    ECanaMboxes.MBOX10.MSGID.all = 0x8000000A;
    ECanaMboxes.MBOX11.MSGID.all = 0x8000000B;
    ECanaMboxes.MBOX12.MSGID.all = 0x8000000C;
    ECanaMboxes.MBOX13.MSGID.all = 0x8000000D;
    ECanaMboxes.MBOX14.MSGID.all = 0x8000000E;
    ECanaMboxes.MBOX15.MSGID.all = 0x8000000F;

    // Write to the MSGID field of RECEIVE mailboxes MBOX16 - 31
    ECanaMboxes.MBOX16.MSGID.all = 0x81111110;
    ECanaMboxes.MBOX17.MSGID.all = 0x81111111;
    ECanaMboxes.MBOX18.MSGID.all = 0x81111112;
    ECanaMboxes.MBOX19.MSGID.all = 0x81111113;
    ECanaMboxes.MBOX20.MSGID.all = 0x81111114;
    ECanaMboxes.MBOX21.MSGID.all = 0x81111115;
    ECanaMboxes.MBOX22.MSGID.all = 0x81111116;
    ECanaMboxes.MBOX23.MSGID.all = 0x81111117;
    ECanaMboxes.MBOX24.MSGID.all = 0x81111118;
    ECanaMboxes.MBOX25.MSGID.all = 0x81111119;
    ECanaMboxes.MBOX26.MSGID.all = 0x8111111A;
    ECanaMboxes.MBOX27.MSGID.all = 0x8111111B;
    ECanaMboxes.MBOX28.MSGID.all = 0x8111111C;
    ECanaMboxes.MBOX29.MSGID.all = 0x8111111D;
    ECanaMboxes.MBOX30.MSGID.all = 0x8111111E;
    ECanaMboxes.MBOX31.MSGID.all = 0x8111111F;

    // Configure Mailboxes 0-15 as Tx, 16-31 as Rx
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANMD.all = 0xFFFF0000;

    // Enable all Mailboxes */
    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
    ECanaRegs.CANME.all = 0xFFFFFFFF;

    // Specify that 8 bits will be sent/received
    ECanaMboxes.MBOX0.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX1.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX2.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX3.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX4.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX5.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX6.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX7.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX8.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX9.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX10.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX11.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX12.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX13.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX14.MSGCTRL.bit.DLC = 8;
    ECanaMboxes.MBOX15.MSGCTRL.bit.DLC = 8;

    // Write to the mailbox RAM field of MBOX0 - 15
    ECanaMboxes.MBOX0.MDL.all = 0x12345678;
    ECanaMboxes.MBOX0.MDH.all = 0x13579ace;

    ECanaMboxes.MBOX1.MDL.all = 0x11111111;
    ECanaMboxes.MBOX1.MDH.all = 0x11111111;

    ECanaMboxes.MBOX2.MDL.all = 0x22222222;
    ECanaMboxes.MBOX2.MDH.all = 0x22222222;

    ECanaMboxes.MBOX3.MDL.all = 0x33333333;
    ECanaMboxes.MBOX3.MDH.all = 0x33333333;

    ECanaMboxes.MBOX4.MDL.all = 0x44444444;
    ECanaMboxes.MBOX4.MDH.all = 0x44444444;

    ECanaMboxes.MBOX5.MDL.all = 0x55555555;
    ECanaMboxes.MBOX5.MDH.all = 0x55555555;

    ECanaMboxes.MBOX6.MDL.all = 0x66666666;
    ECanaMboxes.MBOX6.MDH.all = 0x66666666;

    ECanaMboxes.MBOX7.MDL.all = 0x77777777;
    ECanaMboxes.MBOX7.MDH.all = 0x77777777;

    ECanaMboxes.MBOX8.MDL.all = 0x88888888;
    ECanaMboxes.MBOX8.MDH.all = 0x88888888;

    ECanaMboxes.MBOX9.MDL.all = 0x99999999;
    ECanaMboxes.MBOX9.MDH.all = 0x99999999;

    ECanaMboxes.MBOX10.MDL.all = 0xaaaaaaaa;
    ECanaMboxes.MBOX10.MDH.all = 0xaaaaaaaa;

    ECanaMboxes.MBOX11.MDL.all = 0xbbbbbbbb;
    ECanaMboxes.MBOX11.MDH.all = 0xbbbbbbbb;

    ECanaMboxes.MBOX12.MDL.all = 0xcccccccc;
    ECanaMboxes.MBOX12.MDH.all = 0xcccccccc;

    ECanaMboxes.MBOX13.MDL.all = 0xdddddddd;
    ECanaMboxes.MBOX13.MDH.all = 0xdddddddd;

    ECanaMboxes.MBOX14.MDL.all = 0xeeeeeeee;
    ECanaMboxes.MBOX14.MDH.all = 0xeeeeeeee;

    ECanaMboxes.MBOX15.MDL.all = 0xffffffff;
    ECanaMboxes.MBOX15.MDH.all = 0xffffffff;

    // Since this write is to the entire register (instead of a bit
    // field) a shadow register is not required.
///    EALLOW;
///    ECanaRegs.CANMIM.all = 0xFFFFFFFF;

    // Configure the eCAN for self test mode
    // Enable the enhanced features of the eCAN.
///    EALLOW;
///    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
///    ECanaShadow.CANMC.bit.STM = 1;    // Configure CAN for self-test mode
///    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
///    EDIS;

    // Begin transmitting
    for(;;)
    {
//	   ECanaRegs.CANTRR.all=0x0000ffff;
//       while(ECanaRegs.CANTRS.all != 0x00000000 ) {} 
//EALLOW;
       ECanaRegs.CANTRS.all = 0x0000FFFF;  // Set TRS for all transmit mailboxes
       while(ECanaRegs.CANTA.all != 0x0000ffff ) {}  // Wait for all TAn bits to be set..
       ECanaRegs.CANTA.all = 0x0000FFFF;   // Clear all TAn
    }
}

Fullscreen 8004.initboth1.txt Download

#include "DSP2803x_Device.h"     // DSP28 Headerfile Include File
#include "DSP2803x_Examples.h"   // DSP28 Examples Include File

void initboth11(void)
{
    struct ECAN_REGS ECanaShadow;
    EALLOW;     

    ECanaShadow.CANTIOC.all = ECanaRegs.CANTIOC.all;
    ECanaShadow.CANTIOC.bit.TXFUNC = 1;
    ECanaRegs.CANTIOC.all = ECanaShadow.CANTIOC.all;

    ECanaShadow.CANRIOC.all = ECanaRegs.CANRIOC.all;
    ECanaShadow.CANRIOC.bit.RXFUNC = 1;
    ECanaRegs.CANRIOC.all = ECanaShadow.CANRIOC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.SCB = 1;
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    ECanaMboxes.MBOX0.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX1.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX2.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX3.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX4.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX5.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX6.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX7.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX8.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX9.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX10.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX11.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX12.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX13.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX14.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX15.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX16.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX17.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX18.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX19.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX20.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX21.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX22.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX23.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX24.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX25.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX26.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX27.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX28.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX29.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX30.MSGCTRL.all = 0x00000000;
    ECanaMboxes.MBOX31.MSGCTRL.all = 0x00000000;

// TAn, RMPn, GIFn bits are all zero upon reset and are cleared again
//  as a matter of precaution.
    ECanaRegs.CANTA.all = 0xFFFFFFFF;   /* Clear all TAn bits */
    ECanaRegs.CANRMP.all = 0xFFFFFFFF;  /* Clear all RMPn bits */
    ECanaRegs.CANGIF0.all = 0xFFFFFFFF; /* Clear all interrupt flag bits */
    ECanaRegs.CANGIF1.all = 0xFFFFFFFF;

/* Configure bit timing parameters for eCANA*/
    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 1 ;            // Set CCR = 1
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;
    // Wait until the CPU has been granted permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 1 );       // Wait for CCE bit to be set..
    ECanaShadow.CANBTC.all = 0;

    /* The following block is only for 60 MHz SYSCLKOUT. (30 MHz CAN module clock Bit rate = 1 Mbps
       See Note at end of file. */
    ECanaShadow.CANBTC.bit.BRPREG = 2;
    ECanaShadow.CANBTC.bit.TSEG2REG = 1;
    ECanaShadow.CANBTC.bit.TSEG1REG = 6;

    ECanaShadow.CANBTC.bit.SAM = 1;
    ECanaRegs.CANBTC.all = ECanaShadow.CANBTC.all;

    ECanaShadow.CANMC.all = ECanaRegs.CANMC.all;
    ECanaShadow.CANMC.bit.CCR = 0 ;            // Set CCR = 0
    ECanaRegs.CANMC.all = ECanaShadow.CANMC.all;

    // Wait until the CPU no longer has permission to change the configuration registers
    do
    {
      ECanaShadow.CANES.all = ECanaRegs.CANES.all;
    } while(ECanaShadow.CANES.bit.CCE != 0 );       // Wait for CCE bit to be  cleared..

/* Disable all Mailboxes  */
    ECanaRegs.CANME.all = 0;        // Required before writing the MSGIDs

    EDIS;
}

thank you

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how to configure ecan to communicate between two dsp(tms320f28035)