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Trouble using EVA TIMER1 to initiate ADC acquisitions

Traian Mitrache
Prodigy 180 points

I am trying to set up EVA with TIMER1 to start the sequencer and run ADC acquisitions.

Everything seems to work OK, except for the fact that the intervals at which EVASOCs occur (which I am monitoring with a scope) are exactly 5 times longer that what I calculate them to be. Data is collected properly, and what I get coresponds to the data I see at the ADC input while EVASOC pulses are running....

 

Here are my settings:

I am running with HSPCLK set to 75MHz (13.33ns):

SysCtrlRegs.HISPCP.all = 0x1;          // HSPCLK = SYSCLKOUT/2

The Timer is set to 200 and the compare reg is set to 1:

EvaRegs.T1CMPR = 0x001;               // Setup T1 compare value
EvaRegs.T1PR = 200;   

So I would expect an EVASOC event to occur every 13.33ns * 200 = 2.66us

Instead they are occurring at exactly 5 times that: 13.33 us

I checked the values of the CPS bit and ADCCLKPS, and they are 0 and 0x1 respectively, so the clock going to the ADCs should be HSPCLK...without any prescaling..right?

What am I missing here?

  • 0
    Prodigy 180 points

    Well, one week later, and we still haven't figured this thing out. We thing we have several issues to deal with:

    1) The rate we program the EVA TIMER does not corespond to what we see on the EVASOC pin (113).

    2) The rate of the EVASOC does not corespond with the data we see as being acquired.

    This is what we do: we set up the timer, to a certain value, and it turns out that EVASOC is less than that. We measure the rate of EVASOC on the scope, let's say we find it to be 10KHz. Then we take this value, multiply by 1000 and program a signal generator to give us a sinewave, so that if we took 1000 samples at 10KSPS, we would collect exactly ONE cycle of the sinewave. When we look at the acquired data we see several cycles of that sinewave.

    We also noticed that the EVASOCs are occuring for a lot longer that one CYCLE...It's almost like our ISR misses IRQs, and we are sampling for a longer period of time than one cycle.

    Data is collected in internal RAM

    We took timestamps at the begining and end of the ISR, and it seems like it took 10us to go though it.

    All this is being done with the JTAG emulator...could the JTAG be slowing everything down? How to get around it then?