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Original question:

TMS320F28379D: Can someone show me the code for ADC and DAC synchronization with F2837xD ?

TMS320F28379D: SPI communication beyond 16 bits

alpha beta
Prodigy 80 points

Part Number: TMS320F28379D

Hello,

Recently I try to set up the communication of F28379D launchpad board with an external DAC evaluation board from Ti ( ADC8814EVM ).

I was puzzled by how to get 18 bits SPI communication with ADC8814, as required by its specification for some time.  The additional 2 bits are used to select DAC channels.

There are some examples from Ti CCS. However, these examples are not that easy for me to understand as I am still a beginner .

I find that there is a relative easy way to use the functions from the example ( spi_ex1_loopback.c ) in CCS as following,

"SPI_writeDataNonBlocking(SPIA_BASE, rData);

 SPI_writeDataNonBlocking(SPIA_BASE, sData);

 rData = SPI_readDataBlockingNonFIFO(SPIA_BASE);

 sData = SPI_readDataBlockingNonFIFO(SPIA_BASE);"

where we can repeat the function "SPI_writeDataNonBlocking" to transmit bits twice. One can select the bit width with SPI configuration function to 9 for each transmission.

I have checked the code with an oscilloscope. it works.  The SPITEA signal which doesn't disable the transmission after the the first writing. Therefore, the external DAC board can recognize properly. 

Although it works, there is an unclear point it me: 

What is the function of the  "SPI_readDataBlockingNonFIFO" ? I find it is also essential. One "SPI_writeDataNonBlocking" has to linked to one "SPI_readDataBlockingNonFIFO(SPIA_BASE);".

Best,

Alpha Beta

 

  • 0
    TI__Guru 55700 points

    Hi,

    These functions are defined in spi.h ins driverlib folder.

    SPI_readDataBlockingNonFIFO      -      This function should be only in non-FIFO mode

                                                                     This function waits (polls) for data to be received and then reads it from SPIRXBUF register

    SPI_writeDataNonBlocking              -      This function can be used in both non-FIFO and FIFO mode

                                                             -       This functions writes to SPITXBUF without checking whether SPITXBUF is empty.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Prodigy 80 points

    Thanks for the nice explanation. 

    Additional question: The SPISTE signal is very important. How is this signal controlled in the timing of SPI communication.  I find if I do this way:

    "SPI_writeDataNonBlocking

    SPI_readDataBlockingNonFIFO

    SPI_writeDataNonBlocking

    SPI_readDataBlockingNonFIFO"

    it would be two communication events instead of one communication event. 

    Best,

    Alpha Beta

  • 0 in reply to alpha beta
    TI__Mastermind 32655 points

    Hi,

    The SPISTE pin is controlled by the master SPI. If you have configured the GPIO as SPISTE pin, the GPIO will controlled by the SPI hardware. The pin goes low before transmitting the first bit and goes high after transmitting the last bit. Whether you are using FIFO mode or non-FIFO mode, the SPISTE is active only while the data is being transmitted.

    You could configure the STE pins as normal GPIO and turn it high or low via software.

    Regards,

    Veena