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TMS320F28388S: how to configure 60MHz clock for USB

Strong ZHANG
Expert 4700 points

Part Number: TMS320F28388S
Other Parts Discussed in Thread: C2000WARE

Hi Team,

My customer want to configure 60Mhz clock for USB at F28388, from the TRM that the clock source for USB is either CMCLK or CPU1.SYSCLK, but they require that CMCLK is configure to 125MHz, and CPU1.SYSCLK  is configure to 200MHz,  in this case how to configure 60MHz clock for USB?

Set up the auxiliary PLL so a 60 MHz output clock is provided to the USB module. This fixed frequency is

required for all USB operations. See the System Control chapter for more details.

  • 0
    TI__Mastermind 37205 points

    Strong,

    Auxiliary clock can be set using the API "SysCtl_setAuxClock" defined in sysctl.c.

    The customer can refer any USB example included in C2000Ware for F2838x.

    The following code snippet is used to configure the Aux clock to 60 MHz.
      
        SysCtl_setAuxClock(DEVICE_AUXSETCLOCK_CFG_USB);

    Best Regards

    Siddharth

  • 0 in reply to Siddharth Deshpande
    TI__Guru** 117051 points

    Hi Zhang,

    In addition, to your below query -

    from the TRM that the clock source for USB is either CMCLK or CPU1.SYSCLK, but they require that CMCLK is configure to 125MHz, and CPU1.SYSCLK  is configure to 200MHz,  in this case how to configure 60MHz clock for USB?

    USB has two clock input. USB functional clock and USBBITCLK. CMCLK or CPU1.SYSCLK is used for USB functional clock and frq of this will depend on CMCLK or CPU1.SYSCLK frq. USBBITCLK (see in top right corner in "Figure 3-6 Cocking System" need to be 60MHz.

    Hope this is clear.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    TI__Expert 4700 points

    Hi Vivek,

    Below are the customer's requirement:

    CPU1.SYSCLK: 200MHz,  CMCLK: 125MHz,

    USBBITCLK: 60MHz,  Ethercat clock: 100MHz,

    is it ok to configure the PLL and divider to meet all the requirement above? if YES, how to do the configuration for both AUL PLL and SYS PLL?

    If NOT, we are thinking about using the below configuration to achieve, which set CMCLK to 120 MHz, and the clock source for Ethercat come from SYSPLL clock, but still use CM core to control Ethercat.

    Is it ok to do this configuration below and everything can work reliability?

  • 0 in reply to Strong ZHANG
    TI__Guru** 117051 points

    Yes, this configuration should be fine. When using EtherCAT, please make sure you are following the clocking recommendation provided in EtherCAT chapter. One of the recommendation is to use same 25MHz clock as Input clock for device and EtherCAT PHY.

    Regards,

    Vivek Singh