TMS320F28377D: EMIF: EMxWAIT and WAIT state consideration?

Hi,

For EMIF with EW = 1 (EMxWAIT activated, with E = 5 ns) how should the below piece of information (a and b) be interpreted in relation to the EMxWAIT ?
      a) seem to indicate that granularity of the « sampling/evaluation» is 16*E of EMxWAIT
      b) seem to indicate that the EMxWAIT is evaluated after the EMIF transfer is closed
Are those 2 assumptions correct?

Not exactly.

a) 16*E granularity is not for sampling but that is timeout time hence it has been included in MIN and MAX pulse width of WAIT signal.

b) This is also not correct. WAIT can not be evaluated after transfer is closed. EMIF transfer has SETP+STROBE+HOLD and WAIT is evaluated during STROBE time.

a) According to datasheet data below the EMIF « sample/evaluate» EMxWAIT (after the EMxOE/EMxWE  falling edge? At the end of the strobe?) every 16*E (ie 80 ns) until EMxWAIT is found desactivated.

EMxOE/EMxWE falling edge is not end of STROBE cycle but start of STROBE cycle.

The EMIF considered that the transfer is closed if one of the below condition is TRUE:
     - The SLAVE has effectively desactivated EMxWAIT before the EMIF « sample/evaluate» it next time.
     - The EMIF has evaluated that EWC = MEWC, which means that the SLAVE has exceeded the maximum WAIT state allowed.

This is correct.

b) The EMIF meets the below READ/WRITE timing between EMxWAIT de-activation done by SLAVE and the EMxOE/EMxWE rising edge.
Those timings need to meet a maximum time of 5*E + 15 (ie 40 ns).

Yes, this is output switching Characteristics meaning device will have that much delay between two transition.

Regards,

Vivek Singh

Hi,

Thanks for yours responses, 

1)

Vivek Singh said:

a) 16*E granularity is not for sampling but that is timeout time hence it has been included in MIN and MAX pulse width of WAIT signal.

So timings 10 and 24 of the Datasheet describe the case where EMxWAIT signal is never de-asserted and the EMIF timeout is reach ?

If it is right, it could be relevant to precise it into the datasheet.

2)

Vivek Singh said:

b) This is also not correct. WAIT can not be evaluated after transfer is closed. EMIF transfer has SETP+STROBE+HOLD and WAIT is evaluated during STROBE time

When the STROBE phase is engaged, at which moment the EMIF will start to sample the EMxWAIT signal to detect if extra strobe cycles are requested by the slave ?

- Just after the falling edge of the EMxOE/EMxWE signal ?

- After a time set after the falling edge of the EMxOE/EMxWE signal ? if yes what is this time ?

3)

if the strobe phase is equal to 15 ns and the EMIF detects EMxWAIT asserted after 5 ns, it will add extra strobe cycles until EMxWAIT is sampled de-asserted by the EMIF.

But then the EMIF will finish the 10 ns of the strobe phase before to enter into the HOLD phase ? or this time will be shorted ?

Vivek Singh said:

b) The EMIF meets the below READ/WRITE timing between EMxWAIT de-activation done by SLAVE and the EMxOE/EMxWE rising edge.
Those timings need to meet a maximum time of 5*E + 15 (ie 40 ns).

Yes, this is output switching Characteristics meaning device will have that much delay between two transition.

4)

So here it is the common case where EMxWAIT signal is de-asserted before timeout defined at 1) ?

Regards,

Alexandre.

Hi,

Thanks again for your response, it is now clear to me.

tlee said:

DA_AGL

4)

So here it is the common case where EMxWAIT signal is de-asserted before timeout defined at 1) ?

I don't understand this question. Are you asking about this timing diagram?

Yes it is exactly this, timings 11 and 25.

I suppose that these times define the case where EMxWAIT is de-asserted before the EMIF timeout as described in timings 10 and 24.

Regards,

Alexandre.