CCS/TMS320F28377S: I2C STP Bit Never Detected

Cameron Graves

Part Number: TMS320F28377S

Tool/software: Code Composer Studio

Hello,

I am not detecting a stop bit after my I2C write function. I send the message with a stop. I2cMsg.MsgStatus = I2C_MSGSTAT_SEND_WITHSTOP (0x0010). At the end of I2C write function, I use the following code:

I2cbRegs.I2CMDR.all = 0x6E20;

return I2C_SUCCESS;

That line of code should set the start and stop bits (as well as others). Instead, using a break point, I find that I2cRegs.I2CMDR.all = 0x4620. These two hex values differ in the start and stop bits.

I understand the start bit being reset after initiating the start, but it seems that the stop bit never actually gets set. This was noticed because the bus busy bit is set and I don't enter my "stop bit detected" portion of my code. I am able to toggle it manually in the expressions window, but it takes more than one attempt.

Any insight is appreciated.

Thank you,

Cameron

over 5 years ago

0 Whitney Dewey over 5 years ago

TI__Guru 53745 points

Where are you putting the breakpoint? Are you saying as soon as you step over the MDR = 0x6E20 line it shows 0x4620 or is it later in the execution? Even so, if you have both free run mode enabled in the I2C registers and continuous update mode enabled in the CCS registers view, it may be the case that it has in fact sent both start and stop already and cleared the bits--have not personally tested this theory though.

Another thing to check is if you're getting a NACK. I believe the hardware clears the STP bit in case of a NACK but holds the SCL line low which may account for the BB status being set. Is the NACK bit set? There is some info on handling it here:

https://processors.wiki.ti.com/index.php/I2C_Tips#Hardware_Response_to_a_NACK

Do you have access to a logic analyzer or oscilloscope you could use to observe what is actually happening on the signals?

Whitney

0 Cameron Graves over 5 years ago in reply to Whitney Dewey

Prodigy 230 points

Hi Whitney,

I am placing the breakpoint just before setting MDR = 0x6E20. As soon as I step over, MDR = 0x4620. It looks like the NACK bit is set as soon as I step over this line of code.

I am using an oscilloscope and can see that SCL is held low. Thanks for the info, I'll read through the NACK handling.

Thank you,

Cameron

0 Whitney Dewey over 5 years ago in reply to Cameron Graves

TI__Guru 53745 points

Hi Cameron,

Were you able to resolve this issue?

Whitney

0 Cameron Graves over 5 years ago in reply to Whitney Dewey

Prodigy 230 points

Hi Whitney,

I am all set.

Thanks for the help,

Cameron

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CCS/TMS320F28377S: I2C STP Bit Never Detected