Hi Team,
This is customer request and I would be very happy if you can support.
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We used the TQFP-100 case Delfino DSP with the code TMS320F28377SPZPS. There are two ADCs on DSP. The total number of entries of these is 7 in differential mode and 14 in single ended mode. In single ended mode, ADCs work at 12-bit resolution. It works in 16-bit resolution in Differential mode. We want to use ADCs in diff mode at 16-bit resolution. Our problem with ADCs is as follows; There is conflicting information about ADC in the Delfino technical document. In order to avoid problems in the future, we need to clarify the issue today.
The first page of the document says that the analog subsystem supports 16-bit diff, 12-bit single ended modes. No additional information was provided according to the number of pins.
There is a comparison table on page 9, and it seems that the processor we selected supports 16 and 12-bit ADC, includes two separate ADCs, supports diff and single ended modes.
In section 5.10, page 96, there is a block diagram of the analog subsystem for 377-pin DSPs. ADCs appear to be 12 or 16-bit selectable. There is generally no problematic situation.
There is similar information for 176-pin PTP on page 97 and again no problem.
On page 98 there is information for the 100-pin PZP sleeve we have selected. Only 12-bit is supported here. There is no 16-bit option. This information contradicts previous pages. Is the information given here correct? Or did I get it wrong here?
In section 5.10.1 ADC, there is no special case regarding 100-pin. It seems possible to run 12 or 16-bit.
My request is that you provide me with certainty as to whether the information given on page 98 is incorrect.
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Thanks in advance
Best Regards
Furkan Sefiloglu
