TMS320F280049C: Multiple CMPSS issue

When you say "CMPSS3 is not working any more," is it both the output on GPIO28 and the trip of PWM that stop working or is it just one or the other? Do the COMPSTS registers show the correct status? Can you elaborate?

Nothing in the code is jumping out at me as an issue. Do you mind sharing the part of your PWM configuration related to the trip configuration?

Whitney

Hello Whitney,

Thank you to take care of our issue.

When CMPSS3 is alone, Both GPIO28 and Epwm trip together

Further to your information, I've made some experiments without and with Comp1Init()

< or > is the comparator condition

                      1    3 COMPSTS1  COMPSTS3 GPIO28 EPwm 

Hi Francois,

For debugging purposes, let's try to isolate the comparator and epwm connection for now and concentrate only on the comparator. If you route CMPSS1 and CMPSS3 only to output XBARs, do they work as intended when initialized together and separately?

Hello Frank,

Thanks for you reply. I've investigate a little more on comparators but I prefer to have your opinion ?

I've Added a small delay between turning on clock and configuration and thing are working now.

Here is what I've Added, now CMPSS seems to be initialized correctly.

void Comp3Init(void)
{
//! Initialize Output voltage comparator.
//!
//! \param None.
//!
//! CMPSS3
//!
//! \return 0 None.
uchar i;
EALLOW;
CpuSysRegs.PCLKCR14.bit.CMPSS3 = 1;               /* 1: Module clock is turned-on. */
i = 0;
do
  i ++;
while (i != 0);
Cmpss3Regs.COMPCTL.bit.COMPDACE = 1;              /* 1 Comparator/DAC enabled */
/* Comparator High */
Cmpss3Regs.COMPCTL.bit.COMPHSOURCE = 0;           /* 0 Inverting input of comparator driven by internal DAC */
Cmpss3Regs.COMPDACCTL.bit.SELREF = 0;             /* 0 VDDA is the voltage reference for the DAC */
Cmpss3Regs.DACHVALS.bit.DACVAL = 2048;//DataFlash.VOutMax * VOUTGAIN;
Cmpss3Regs.COMPCTL.bit.CTRIPHSEL = 0;             /* 0 Asynchronous comparator output drives CTRIPH */
Cmpss3Regs.COMPCTL.bit.CTRIPOUTHSEL = 0;          /* 0 Asynchronous comparator output drives CTRIPOUTH */
/* Input high = B3 */
AnalogSubsysRegs.CMPHPMXSEL.bit.CMP3HPMXSEL = 3;  /* 3 : B3 High Positive */
/* Trip zone on EPwmA */
EPwmXbarRegs.TRIP7MUX0TO15CFG.bit.MUX4 = 0;       /* Configure TRIP5 to be CTRIP3H */
EPwmXbarRegs.TRIP7MUXENABLE.bit.MUX4 = 1;         /* 1: Respective output of Mux0 is enabled to drive the TRIP5 of EPWM-XBAR */
/* Output to pin */
OutputXbarRegs.OUTPUT5MUX0TO15CFG.bit.MUX4 = 0;   /* 00 : Select .0 input for Mux0 */
OutputXbarRegs.OUTPUT5MUXENABLE.bit.MUX4 = 1;     /* 1: Respective output of Mux0 is enabled to drive the OUTPUT5 of OUTPUT-XBAR */
//GpioDataRegs.GPASET.bit.GPIO28 = 0;
GpioCtrlRegs.GPADIR.bit.GPIO28 = 1;               /* 1: The pin is an output */
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;
GpioCtrlRegs.GPAGMUX2.bit.GPIO28 = 1;
EDIS;
} 

Hi Francois,

I'm glad you have found a workaround but the solution is a bit odd. I have never seen this. I wonder if it has something to do with the read-modify-write of PCLKCR14 since it contains clock turn-on for all the CMPSS. If you can, please try a few experiments below so we can figure out what's happening.

1. If you go back to your original code without the delay, after you enable both CMPSS1 and CMPSS3, can you check the COMPDACE bit of both CMPSS to see if they were indeed set to 1?

2. To confirm this is not a read-modify-write issue, when enabling the clocks for CMPSS1 and CMPSS3 using PCLKR14, instead of using CpuSysRegs.PCLKCR14.bit.CMPSS1 and CpuSysRegs.PCLKCR14.bit.CMPSS3, use CpuSysRegs.PCLKCR14.all. In CMPSS1 config code, write a value that only turns on CMPSS1. In the CMPSS3 code, write this to a value that turns on both CMPSS1 and CMPSS3.

Hi Frank,

Further to your advice, I've test the following :

1) 

Remove my workaround

When I initialized both CMPSS (1 then 3), 3 is not working

PCLK14 = 0x0000 0005 (Both CMPSS are clocked)

 Cmpss1Regs.COMPCTL.COMPDACE = 1  -> OK

 Cmpss3Regs.COMPCTL.COMPDACE = 0  -> Bad (this is the problem)

2)

Remove my workaround

Put CpuSysRegs.PCLKCR14.all = 0x0001; in Comp1Init()

Put CpuSysRegs.PCLKCR14.all = 0x0005; in Comp3Init()

PCLK14 = 0x0000 0005 (Both CMPSS are clocked)

Cmpss1Regs.COMPCTL.COMPDACE = 1  -> OK

 Cmpss3Regs.COMPCTL.COMPDACE = 0  -> Bad

I think the problem is a problem of stabilization of the clock, if I execute the program step by step with the debugger then it's OK.

Best regards

francois

Hi Francois,

Thanks for performing the additional debug. Yes you are right, this is looking like a clock delay issue. This behavior is unexpected. Even if there was a clocking delay before the modules can be configured, i would expect both CMPSS1 and CMPSS3 to require the same delay but based on your analysis, CMPSS1 does not require a delay while CMPSS3 does.

If you don't mind, can you ran one more experiment? I want to confirm which CMPSS exhibit this behavior. Can you repeat the same experiment for all 7 CMPSS? Turn on the clock for each CMPSS, write to COMPDACE and check if it was set to 1.

Hello Frank,

I've done the Following and here here the results :

Hi Francois,

Thanks for the additional debug. This is interesting. Let me perform some local investigation and get back to you. Expect a reply by next week Tuesday.