Part Number: TMS320F28069
Other Parts Discussed in Thread: C2000WARE
Hi, I am trying to configure CLA on TMS320F28069.
But,When I Perform Build Operation, It Shows Error of which i Have Shared Screenshot.
Please Help me to understand and rectify it.
Thank you
;//########################################################################### ;// ;// FILE: F2806x_Cla.asm ;// ;// TITLE: CLA Assembly Code. ;// ;// This file contains the CLA assembly code. When building the project ;// containing this file, use C28x codegen V5.2.0 or later with the switch ;// --cla_support=cla0 ;// ;//########################################################################### ;// $TI Release: F2806x Support Library v2.04.00.00 $ ;// $Release Date: Mon May 27 06:46:38 CDT 2019 $ ;// $Copyright: ;// Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/ ;// ;// Redistribution and use in source and binary forms, with or without ;// modification, are permitted provided that the following conditions ;// are met: ;// ;// Redistributions of source code must retain the above copyright ;// notice, this list of conditions and the following disclaimer. ;// ;// Redistributions in binary form must reproduce the above copyright ;// notice, this list of conditions and the following disclaimer in the ;// documentation and/or other materials provided with the ;// distribution. ;// ;// Neither the name of Texas Instruments Incorporated nor the names of ;// its contributors may be used to endorse or promote products derived ;// from this software without specific prior written permission. ;// ;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR ;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT ;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, ;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT ;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, ;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY ;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE ;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;// $ ;//########################################################################### ;// Include variables and constants that will be shared in the ;// C28x C-code and CLA assembly code. This is accomplished by ;// using .cdecls to include a C-code header file that contains ;// these variables and constants .cdecls C,LIST,"CLAShared.h" ;// To include an MDEBUGSTOP (CLA breakpoint) as the first instruction ;// of each task, set CLA_DEBUG to 1. Use any other value to leave out ;// the MDEBUGSTOP instruction. CLA_DEBUG .set 1 ;// CLA code must be within its own assembly section and must be ;// even aligned. Note: since all CLA instructions are 32-bit ;// this alignment naturally occurs and the .align 2 is most likely ;// redundant .sect "Cla1Prog" .align 2 _Cla1Prog_Start: _Cla1Task1: MSTOP MNOP MNOP MNOP _Cla1T1End: _Cla1Task2: .if CLA_DEBUG == 1 MDEBUGSTOP .endif ;============================================== ; This task logs the last NUM_DATA_POINTS ; ADCRESULT1 values in the array VoltageCLA ; ; When the last element in the array has been ; filled, the task will go back to the ; the first element. ; ; Before starting the ADC conversions, force ; Task 8 to initialize the ConversionCount to zero ; ;============================================== MMOVZ16 MR0, @_ConversionCount ;1 Current Conversion MMOV16 MAR1, MR0, #_VoltageCLA ;2 Point to VoltageCLA[ConversionCount] MUI16TOF32 MR0, MR0 ;3 Convert count to float32 MADDF32 MR0, MR0, #1.0 ;4 Add 1 to conversion count MCMPF32 MR0, #NUM_DATA_POINTS.0 ;5 Compare count to max MF32TOUI16 MR0, MR0 ;6 Convert count to Uint16 MNOP ;7 Wait till I8 to read result MMOVZ16 MR2, @_AdcResult.ADCRESULT1 ;8 Read ADCRESULT1 MMOV16 *MAR1, MR2 ; Store ADCRESULT1 MBCNDD _RestartCount, GEQ ; If count >= NUM_DATA_POINTS MMOVIZ MR1, #0.0 ; Always executed: load MR1 with 0 MNOP MNOP MMOV16 @_ConversionCount, MR0 ; If branch not taken, store current count MSTOP _RestartCount MMOV16 @_ConversionCount, MR1 ; If branch taken, restart count MSTOP MNOP MNOP MNOP _Cla1T2End: _Cla1Task3: MSTOP MNOP MNOP MNOP _Cla1T3End: _Cla1Task4: MSTOP MNOP MNOP MNOP _Cla1T4End: _Cla1Task5: MSTOP MNOP MNOP MNOP _Cla1T5End: _Cla1Task6: MSTOP MNOP MNOP MNOP _Cla1T6End: _Cla1Task7: MSTOP MNOP MNOP MNOP _Cla1T7End: _Cla1Task8: ;============================================== ; This task initializes the ConversionCount ; to zero ;============================================== MMOVIZ MR0, #0.0 MMOV16 @_ConversionCount, MR0 MSTOP _Cla1T8End: _Cla1Prog_End: .end .include "CLAShared.h" ; ; End of File ;
//########################################################################### // // FILE: CLAShared.h // // TITLE: CLA and CPU shared variables and constants // //########################################################################### // $TI Release: F2806x Support Library v2.04.00.00 $ // $Release Date: Mon May 27 06:46:38 CDT 2019 $ // $Copyright: // Copyright (C) 2009-2019 Texas Instruments Incorporated - http://www.ti.com/ // // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions // are met: // // Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. // // Redistributions in binary form must reproduce the above copyright // notice, this list of conditions and the following disclaimer in the // documentation and/or other materials provided with the // distribution. // // Neither the name of Texas Instruments Incorporated nor the names of // its contributors may be used to endorse or promote products derived // from this software without specific prior written permission. // // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // $ //########################################################################### #ifndef CLA_SHARED_H #define CLA_SHARED_H #ifdef __cplusplus extern "C" { #endif // // Included Files // #include "IQmathLib.h" #include "DSP28x_Project.h" // // Defines // #define NUM_DATA_POINTS 20 extern Uint16 ConversionCount; extern Uint16 VoltageCLA[NUM_DATA_POINTS]; // // The following are symbols defined in the CLA assembly code // Including them in the shared header file makes them // .global and the main CPU can make use of them. // extern Uint32 Cla1Task1; extern Uint32 Cla1Task2; extern Uint32 Cla1Task3; extern Uint32 Cla1Task4; extern Uint32 Cla1Task5; extern Uint32 Cla1Task6; extern Uint32 Cla1Task7; extern Uint32 Cla1Task8; extern Uint32 Cla1Prog_Start; extern Uint32 Cla1T1End; extern Uint32 Cla1T2End; extern Uint32 Cla1T3End; extern Uint32 Cla1T4End; extern Uint32 Cla1T5End; extern Uint32 Cla1T6End; extern Uint32 Cla1T7End; extern Uint32 Cla1T8End; #ifdef __cplusplus } #endif /* extern "C" */ #endif // end of CLA_SHARED definition // // End of File //
/*==================================================================================*/
/* User specific Linker command file for running from FLASH */
/*==================================================================================*/
/* FILE: F2806x_FLASH_DeadBandPWM.CMD
/* */
/* Description: Linker command file for User custom sections targetted to run */
/* from FLASH. */
/* */
/* Target: TMS320F2806x */
/* */
/* Version: 1.0 */
/* */
/*----------------------------------------------------------------------------------*/
/* Copyright Texas Instruments © 2010 */
/*----------------------------------------------------------------------------------*/
/* Revision History: */
/*----------------------------------------------------------------------------------*/
/* Date | Description */
/*----------------------------------------------------------------------------------*/
/* 01/11/11 | Release 1.0 */
/*----------------------------------------------------------------------------------*/
/* Define the memory block start/length for the F2806x
PAGE 0 will be used to organize program sections
PAGE 1 will be used to organize data sections
Notes:
Memory blocks on F2806x are uniform (ie same
physical memory) in both PAGE 0 and PAGE 1.
That is the same memory region should not be
defined for both PAGE 0 and PAGE 1.
Doing so will result in corruption of program
and/or data.
The L0 memory block is mirrored - that is
it can be accessed in high memory or low memory.
For simplicity only one instance is used in this
linker file.
Contiguous SARAM memory blocks or flash sectors can be
be combined if required to create a larger memory block.
*/
MEMORY
{
PAGE 0:
/* Program Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
BOOT_RSVD : origin = 0x000000, length = 0x000050 /* Part of M0, BOOT rom will use this for stack */
progRAM : origin = 0x008000, length = 0x000C00
CLAPROGRAM : origin = 0x009000, length = 0x001000 /* on-chip RAM block L3 */
OTP : origin = 0x3D7800, length = 0x000400 /* on-chip OTP */
FLASHH : origin = 0x3D8000, length = 0x004000 /* on-chip FLASH */
FLASHG : origin = 0x3DC000, length = 0x004000 /* on-chip FLASH */
FLASHF : origin = 0x3E0000, length = 0x004000 /* on-chip FLASH */
FLASHE : origin = 0x3E4000, length = 0x004000 /* on-chip FLASH */
FLASHD : origin = 0x3E8000, length = 0x004000 /* on-chip FLASH */
FLASHC : origin = 0x3EC000, length = 0x004000 /* on-chip FLASH */
FLASHA : origin = 0x3F4000, length = 0x003F80 /* on-chip FLASH */
CSM_RSVD : origin = 0x3F7F80, length = 0x000076 /* Part of FLASHA. Program with all 0x0000 when CSM is in use. */
BEGIN : origin = 0x3F7FF6, length = 0x000002 /* Part of FLASHA. Used for "boot to Flash" bootloader mode. */
CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations in FLASHA */
FPUTABLES : origin = 0x3FD860, length = 0x0006A0 /* FPU Tables in Boot ROM */
IQTABLES : origin = 0x3FDF00, length = 0x000B50 /* IQ Math Tables in Boot ROM */
IQTABLES2 : origin = 0x3FEA50, length = 0x00008C /* IQ Math Tables in Boot ROM */
IQTABLES3 : origin = 0x3FEADC, length = 0x0000AA /* IQ Math Tables in Boot ROM */
BOOTROM : origin = 0x3FF3B0, length = 0x000C10 /* Boot ROM */
RESET : origin = 0x3FFFC0, length = 0x000002 /* part of boot ROM */
VECTORS : origin = 0x3FFFC2, length = 0x00003E /* part of boot ROM */
PAGE 1 :
/* Data Memory */
/* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
/* Registers remain on PAGE1 */
RAMM0 : origin = 0x000050, length = 0x0003B0 /* on-chip RAM block M0 */
RAMM1 : origin = 0x000400, length = 0x000400 /* on-chip RAM block M1 */
dataRAM : origin = 0x008C00, length = 0x001400
CLA1_MSGRAMLOW : origin = 0x001480, length = 0x000080
CLA1_MSGRAMHIGH : origin = 0x001500, length = 0x000080
RAML4 : origin = 0x00A000, length = 0x002000 /* on-chip RAM block L4 */
RAML5 : origin = 0x00C000, length = 0x002000 /* on-chip RAM block L5 */
RAML6 : origin = 0x00E000, length = 0x002000 /* on-chip RAM block L6 */
RAML7 : origin = 0x010000, length = 0x002000 /* on-chip RAM block L7 */
RAML8 : origin = 0x012000, length = 0x002000 /* on-chip RAM block L8 */
FLASHB : origin = 0x3F4000, length = 0x002000
}
SECTIONS
{
/* Allocate program areas: */
.cinit : > FLASHA, PAGE = 0
.pinit : > FLASHA, PAGE = 0
.text : > FLASHA | FLASHC | FLASHD, PAGE = 0
codestart : > BEGIN PAGE = 0
ramfuncs : LOAD = FLASHA,
RUN = progRAM,
LOAD_START(_RamfuncsLoadStart),
LOAD_END(_RamfuncsLoadEnd),
RUN_START(_RamfuncsRunStart),
PAGE = 0
csmpasswds : > CSM_PWL PAGE = 0
csm_rsvd : > CSM_RSVD PAGE = 0
Cla1Prog : LOAD = FLASHE,
RUN = CLAPROGRAM,
LOAD_START(_Cla1funcsLoadStart),
LOAD_SIZE(_Cla1funcsLoadSize),
RUN_START(_Cla1funcsRunStart),
PAGE = 0
/* Allocate uninitalized data sections: */
.stack : > RAMM0, PAGE = 1
.ebss : > dataRAM, PAGE = 1
.esysmem : > dataRAM, PAGE = 1
Cla1ToCpuMsgRAM : > CLA1_MSGRAMLOW, PAGE = 1
CpuToCla1MsgRAM : > CLA1_MSGRAMHIGH, PAGE = 1
Cla1DataRam0 : > RAML4, PAGE = 1
Cla1DataRam1 : > RAML4, PAGE = 1
Cla1DataRam2 : > RAML4, PAGE = 1
#ifdef CLA_C
.scratchpad : > RAML4, PAGE = 1
.bss_cla : > RAML4, PAGE = 1
.const_cla : > RAML4, PAGE = 1
#endif
/* Initalized sections go in Flash */
/* For SDFlash to program these, they must be allocated to page 0 */
.econst : > FLASHA PAGE = 0
.switch : > FLASHA PAGE = 0
/* Allocate IQ math areas: */
IQmath : > FLASHA PAGE = 0 /* Math Code */
IQmathTables : > IQTABLES PAGE = 0, TYPE = NOLOAD /* Math Tables In ROM */
/* Uncomment the section below if calling the IQNexp() or IQexp()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables2 : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
}
*/
/* Uncomment the section below if calling the IQNasin() or IQasin()
functions from the IQMath.lib library in order to utilize the
relevant IQ Math table in Boot ROM (This saves space and Boot ROM
is 1 wait-state). If this section is not uncommented, IQmathTables2
will be loaded into other memory (SARAM, Flash, etc.) and will take
up space, but 0 wait-state is possible.
*/
/*
IQmathTables3 : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
{
IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
}
*/
.reset : > RESET, PAGE = 0, TYPE = DSECT
vectors : > VECTORS PAGE = 0, TYPE = DSECT
}
SECTIONS
{
Net_terminals: > dataRAM,PAGE = 1
}
