TMS320F28375D: Local memory combination for CLA1

Hi,

It is okay to combine the LSRAMs and the way you have updated the linker command file looks correct. You need to make sure that all those LSRAMs are assigned to CLA.

If you are using driverlib, MemCfg_setLSRAMMasterSel is the function that sets the owner of the LS RAM (CPU or CLA) and MemCfg_setCLAMemType is the function that configures the memory as data/program.

If you combine LS2,LS3,LS4 as LS2, you need to invoke these functions for each of those LS RAMs. Have you done that?

Regards,
Veena

Hello Veena,

Thanks for reply,

Below are settings done in firmware,

MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1; //RAMLS2
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1; //RAMLS3
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1; //RAMLS4
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; //RAMLS0
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; //RAMLS1
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;

Still the function which we have developed "calc_PR_CLA" malfunction at same specific code line. If we remove that line and put at the separate location of same function it did work. As mentioned in previous post, this function consumed is 2430 bytes memory.
below is highlight of map file for your reference,

0 00009000 _Cla1funcsRunStart
0 00009000 _calc_PR_CLA
0 0000997c _Cla1Task2
0 0000a2bc _Deadtime_gen
0 0000a2f0 _Cla1Task1
0 0000a2f8 _Cla1Task3
0 0000a300 _Cla1Task4
0 0000a308 _Cla1Task5
0 0000a310 _Cla1Task6
0 0000a318 _Cla1Task7
0 0000a320 _Cla1Task8
If you see in above map file you can see start address of _calc_PR_CLA function is start address of RAMLS2, as this function is larger than 2048 bytes it overlap and written in RAMLS3. so can this make problem to program counter during execution.(We have combined RAMLS2, RAMLS3 and RAMLS4).
Or else what can be cause of this type of malfunction, how can we troubleshoot?

Regards,

Dushyant

Hi Dushyant,

Apologies for the delayed response.

I was unable to reproduce the issue. I added some dummy instructions in a CLA task and made the function size more than 0xA00. I combined LS2 and LS3 as a single section, also configured both these RAMs as CLA program memory.

The task was running as expected and did not see any different behavior while moving from LS2 to LS3.

Can you provide us more information on what error you were facing. If possible, share the code so that we could reproduce the issue at our end.

Regards,

Veena

Dear veena,
Thanks for support,

As per your request i can not send you my product code as it is against my company policy,
but i have attached CLA source and header file,  memory allocation file and map file in rar folder for your reference.

Below are settings done in firmware, just for your reference,

MemCfgRegs.LSxMSEL.bit.MSEL_LS2 = 1; //RAMLS2
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS2 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS3 = 1; //RAMLS3
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS3 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS4 = 1; //RAMLS4
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS4 = 1;

MemCfgRegs.LSxMSEL.bit.MSEL_LS0 = 1; //RAMLS0
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS0 = 0;

MemCfgRegs.LSxMSEL.bit.MSEL_LS1 = 1; //RAMLS1
MemCfgRegs.LSxCLAPGM.bit.CLAPGM_LS1 = 0;

in CLA source file at Line 276: "total_Y = total_Y + CPU_and_CLA.Y_pr[8].yn0;" Code is Malfunctioning.

Regards,

Dushyant Rana

6562.query-cla.rar

Hi Dushyant,

For some reason, I am not able to extract the rar contents. Can you please resend?

What are observing while that line is getting executed? Is the core getting reset? Is the instruction fetch not happening? Is the register/memory access not happening? Is the core returning a different value as the sum?

Regards,

Veena

Dear Veena,

Please find attached files.

Problem we are observing is look like,  instruction fetch not happening or may be memory access not happening.

Please do look in this matter as soon as possible, as we are stuck in this issue for long time.

Regards,

Dushyant RanaCLA_Query.rar

Hi Amtech,

While Veena try to reproduce this issue on our local setup, what I understand from your explanation that if you change the location of these function then it works fine hence it may take multiple iteration. Can you help with below query -

• When it fails  -  what is the address location of this code (total_Y = total_Y + CPU_and_CLA.Y_pr[8].yn0)
• When it pass -  what is the address location of this code (total_Y = total_Y + CPU_and_CLA.Y_pr[8].yn0)

All the RAM blocks are same so it is unlikely that instruction fetch having issue. Could it be the issue with the variables getting overwritten hence it's not working as expected? Have you checked the value of variables in both passing and failing case ?

Regards,

Vivek Singh

Hi Dushyant,

Which compiler version are you using? If not the latest, can you switch to the latest compiler?

I included the cla file you shared in my sample C28x project and ran the code. I also added the following definitions in the .cla file since it was missing:

struct CLA_VARS CLA_vars;
struct CPU_CLA CPU_and_CLA;

uint32_t total_R, total_Y, total_B;

Since I did not have the structs populated with valid values, I updated the variables total_Y and CPU_and_CLA.Y_pr[8].yn0 just before the addition and the variable total_Y  is getting updated with the correct value.

Regards,

Veena

Dear sir,

kindly find attached zip folder.

In this zip file there are two folders one folder is containing assembly and source file of the CLA1 function which cause malfunction and another contains assembly and source file which is working fine.

When it fails  -  the address location of this code (total_Y = total_Y + CPU_and_CLA.Y_pr[8].yn0) is "0094e0"

When it pass -  the address location of this code (total_Y = total_Y + CPU_and_CLA.Y_pr[8].yn0) is "0094fe" 

And the compiler i am using is "TI v18.1.1.LTS".

Regards,

Dushyant Rana

Disambly-Files.rar

Hi Dushyant,

Apologies for the delayed response. We are unable to reproduce the issue. We checked the disassembly files you shared and could not figure out any reason why it is failing.

Are you still facing the issue?

Regards,

Veena

Dear Madam,

We have reconfigured the Local RAM allocation to CLA. After doing that we are not having any problem.

But if with previuos Local RAM configuration still code does fail. So i guess there is some issue with local memory configuration when using CLA.

Thanks and Regards,

Dushyant Rana

Hi Dushyant,

I am not sure if I got it right. For CLA to use the LSRAM, the ownership of the LSRAM has to be set to CLA and the the LSRAM needs to be configured as program memory. I believe you had this configured already.

What change did you add to make it work?

Regards,

Veena

Dear Madam,

Please find attached files. In attached files there are two folders, each folder contain setting of LSRAM allocation and CLA setting used in firmware and it also includes .map file of compiled code. These folders are classified as Failing means firmware fail with this setting and working means firmware is wokirng ok.

Thanks and Regards,

Dushyant RanaConfig-Files.rar

Thanks Dushyant.

I am not able to find any reason why the combined LSRAM is not working and mapping sections to individual LSRAMs is working fine.

Technically, both should not make any difference.

I will check with experts and get back to you if I get the reason. For now, I recommend you to use individual LSRAMs for allocating CLA program memory.

Regards,

Veena