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LAUNCHXL-F28379D: Non-symmetrical Complementary PWM Signals

Part Number: LAUNCHXL-F28379D

I am trying to get two symmetrical complementary PWM signals, but in all deadband modes I get the width of one of the signals more than the other. I figured from the datasheet I cannot use REDDB for both PWMA and PWMB; only one of them and same for FEDDB. Please see the picture attached.

The code I'm using:

// Setup deadtime
// Active high complementary PWMs - Setup the deadband
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = DeadTime/10;
EPwm1Regs.DBFED = DeadTime/10;

  • Your picture did not go through!

  • Here is the code; the duty cycle is set to be 50%, the width of the PWM1A signal is more than that of the PWM1B signal by the deadtime value.

    void InitEPwm1Example()
    {
    // Setup TBCLK
    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
    EPwm1Regs.TBPRD = EPWM_TIMER_TBPRD; // Set timer period
    EPwm1Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Disable phase loading
    EPwm1Regs.TBPHS.half.TBPHS = 0; // Phase is 0
    EPwm1Regs.TBCTR = 0x0000; // Clear counter
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = 0;
    EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;

    // Setup deadtime
    // Active high complementary PWMs - Setup the deadband
    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm1Regs.DBRED = 50;
    EPwm1Regs.DBFED = 50;

    // Setup shadow register load on ZERO
    EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
    EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
    EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

    // Set Compare values
    EPwm1Regs.CMPA.half.CMPA = EPWM_TIMER_TBPRD/2; // Set compare A value
    EPwm1Regs.CMPB.half.CMPB = EPWM_TIMER_TBPRD/2; // Set Compare B value

    // Set actions
    EPwm1Regs.AQCTLA.bit.PRD = AQ_SET; // Clear PWM2A on Period
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Set PWM2A on event A, up count

    // Interrupt where we will change the Compare Values
    EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
    EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
    EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event


    // Information this example uses to keep track
    // of the direction the CMPA/CMPB values are
    // moving, the min and max allowed values and
    // a pointer to the correct ePWM registers
    epwm1_info.EPwm_CMPA_Direction = EPWM_CMP_UP; // Start by increasing CMPA & CMPB
    epwm1_info.EPwm_CMPB_Direction = EPWM_CMP_UP;
    epwm1_info.EPwmTimerIntCount = 0; // Zero the interrupt counter
    epwm1_info.EPwmRegHandle = &EPwm1Regs; // Set the pointer to the ePWM module
    epwm1_info.EPwmMaxCMPA = EPWM_MAX_CMPA; // Setup min/max CMPA/CMPB values
    epwm1_info.EPwmMinCMPA = EPWM_MIN_CMPA;
    epwm1_info.EPwmMaxCMPB = EPWM_MAX_CMPB;
    epwm1_info.EPwmMinCMPB = EPWM_MIN_CMPB;
    }

  • Your picture still did not go through for some reason but I did write an example for this and put it online for you to try out.

    I put all the different types of deadband modes in it:

    http://dev.ti.com/tirex/explore/node?node=AFBS.pxfnsxPg24pB7C85w__gYkahfz__LATEST

    Nima