Part Number: LAUNCHXL-F28379D
Other Parts Discussed in Thread: TIDA-010054
i am using a proportional controller as a closed-loop for the dual active bridge where the phase shift is controlled between two h bridges.
however, sometimes the controller giving zero output in between events and going to instability. I am attaching code for the file.
/*
* Academic License - for use in teaching, academic research, and meeting
* course requirements at degree granting institutions only. Not for
* government, commercial, or other organizational use.
*
* File: stab_CL_20khz.c
*
* Code generated for Simulink model 'stab_CL_20khz'.
*
* Model version : 1.166
* Simulink Coder version : 9.3 (R2020a) 18-Nov-2019
* C/C++ source code generated on : Thu Jun 25 01:29:40 2020
*
* Target selection: ert.tlc
* Embedded hardware selection: Texas Instruments->C2000
* Code generation objectives: Unspecified
* Validation result: Not run
*/
#include "stab_CL_20khz.h"
#include "stab_CL_20khz_dt.h"
/* Private macros used by the generated code to access rtModel */
#ifndef rtmSetTFinal
# define rtmSetTFinal(rtm, val) ((rtm)->Timing.tFinal = (val))
#endif
#ifndef UCHAR_MAX
#include <limits.h>
#endif
#if ( UCHAR_MAX != (0xFFFFU) ) || ( SCHAR_MAX != (0x7FFF) )
#error Code was generated for compiler with different sized uchar/char. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif
#if ( USHRT_MAX != (0xFFFFU) ) || ( SHRT_MAX != (0x7FFF) )
#error Code was generated for compiler with different sized ushort/short. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif
#if ( UINT_MAX != (0xFFFFU) ) || ( INT_MAX != (0x7FFF) )
#error Code was generated for compiler with different sized uint/int. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif
#if ( ULONG_MAX != (0xFFFFFFFFUL) ) || ( LONG_MAX != (0x7FFFFFFFL) )
#error Code was generated for compiler with different sized ulong/long. \
Consider adjusting Test hardware word size settings on the \
Hardware Implementation pane to match your compiler word sizes as \
defined in limits.h of the compiler. Alternatively, you can \
select the Test hardware is the same as production hardware option and \
select the Enable portable word sizes option on the Code Generation > \
Verification pane for ERT based targets, which will disable the \
preprocessor word size checks.
#endif
/* Skipping ulong_long/long_long check: insufficient preprocessor integer range. */
void InitAdcC (void);
void config_ADCC_SOC0 (void);
/* Invariant block signals (default storage) */
const ConstB_stab_CL_20khz_T stab_CL_20khz_ConstB = {
251658240 /* '<S1>/Data Type Conversion4' */
};
/* Block signals (default storage) */
B_stab_CL_20khz_T stab_CL_20khz_B;
/* Block states (default storage) */
DW_stab_CL_20khz_T stab_CL_20khz_DW;
/* Real-time model */
RT_MODEL_stab_CL_20khz_T stab_CL_20khz_M_;
RT_MODEL_stab_CL_20khz_T *const stab_CL_20khz_M = &stab_CL_20khz_M_;
extern uint16_T MW_adcCInitFlag;
void isr_int1pie3_task_fcn(void);
extern void configureGPIOExtInterrupt(void);
void isr_int1pie3_task_fcn(void);
uint16_T MW_adcCInitFlag = 0;
/* Hardware Interrupt Block: '<Root>/C28x Hardware Interrupt1' */
void isr_int1pie3_task_fcn(void)
{
/* Call the system: <Root>/PI_Controller_ISR */
{
/* Reset subsysRan breadcrumbs */
srClearBC(stab_CL_20khz_DW.PI_Controller_ISR_SubsysRanBC);
/* S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' */
/* Output and update for function-call system: '<Root>/PI_Controller_ISR' */
{
int32_T tmp;
/* Asynchronous task reads absolute time. Data (absolute time)
transfers from low priority task (base rate) to high priority
task (asynchronous rate). Double buffers are used to ensure
data integrity.
-- rtmL2HLastBufWr is the buffer index that is written last.
*/
stab_CL_20khz_M->Timing.clockTick1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTick
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
stab_CL_20khz_M->Timing.clockTickH1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTickH
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
/* S-Function (c2802xadc): '<S1>/Voltage Vout_FB' */
{
/* Internal Reference Voltage : Fixed scale 0 to 3.3 V range. */
/* External Reference Voltage : Allowable ranges of VREFHI(ADCINA0) = 3.3 and VREFLO(tied to ground) = 0 */
stab_CL_20khz_B.VoltageVout_FB = (AdccResultRegs.ADCRESULT0);
}
/* DataTypeConversion: '<S1>/Data Type Conversion' */
stab_CL_20khz_B.DataTypeConversion = (int32_T)
stab_CL_20khz_B.VoltageVout_FB << 12U;
/* Sum: '<S1>/Sum1' */
stab_CL_20khz_B.Sum1 = 2514944L - stab_CL_20khz_B.DataTypeConversion;
/* S-Function (stiiqmath_iqmpy): '<S1>/IQN x IQN' */
/* C28x IQmath Library (stiiqmath_iqmpy) - '<S1>/IQN x IQN' */
{
stab_CL_20khz_B.IQNxIQN = _IQ24mpy (stab_CL_20khz_B.Sum1,
stab_CL_20khz_ConstB.DataTypeConversion4);
}
/* Saturate: '<S1>/Saturation' */
tmp = stab_CL_20khz_B.IQNxIQN;
if (tmp > 8388608L) {
stab_CL_20khz_B.Saturation = 8388608L;
} else if (tmp < 0L) {
stab_CL_20khz_B.Saturation = 0L;
} else {
stab_CL_20khz_B.Saturation = tmp;
}
/* End of Saturate: '<S1>/Saturation' */
/* Sum: '<S1>/Sum2' incorporates:
* Constant: '<S1>/Constant2'
*/
stab_CL_20khz_B.Sum2 = (int32_T)floor((2.0 - (real_T)
stab_CL_20khz_B.Saturation * 5.9604644775390625E-8) * 1.6777216E+7);
/* Gain: '<S1>/Gain' */
stab_CL_20khz_B.Gain = __IQmpy(625L, stab_CL_20khz_B.Sum2, 5);
/* S-Function (c2802xpwm): '<S1>/ePWM_3' */
EPwm3Regs.TBPHS.bit.TBPHS = (stab_CL_20khz_B.Gain >> 16);
/* Sum: '<S1>/Sum3' */
stab_CL_20khz_B.Sum3 = stab_CL_20khz_B.Gain - 327680000L;
/* S-Function (c2802xpwm): '<S1>/ePWM_4' */
EPwm4Regs.TBPHS.bit.TBPHS = (stab_CL_20khz_B.Sum3 >> 16);
stab_CL_20khz_DW.PI_Controller_ISR_SubsysRanBC = 4;
}
/* End of Outputs for S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' */
}
}
/* Model step function */
void stab_CL_20khz_step(void)
{
/* External mode */
rtExtModeUploadCheckTrigger(1);
{ /* Sample time: [0.2s, 0.0s] */
rtExtModeUpload(0, (real_T)stab_CL_20khz_M->Timing.taskTime0);
}
/* signal main to stop simulation */
{ /* Sample time: [0.2s, 0.0s] */
if ((rtmGetTFinal(stab_CL_20khz_M)!=-1) &&
!((rtmGetTFinal(stab_CL_20khz_M)-stab_CL_20khz_M->Timing.taskTime0) >
stab_CL_20khz_M->Timing.taskTime0 * (DBL_EPSILON))) {
rtmSetErrorStatus(stab_CL_20khz_M, "Simulation finished");
}
if (rtmGetStopRequested(stab_CL_20khz_M)) {
rtmSetErrorStatus(stab_CL_20khz_M, "Simulation finished");
}
}
/* Update absolute time for base rate */
/* The "clockTick0" counts the number of times the code of this task has
* been executed. The absolute time is the multiplication of "clockTick0"
* and "Timing.stepSize0". Size of "clockTick0" ensures timer will not
* overflow during the application lifespan selected.
* Timer of this task consists of two 32 bit unsigned integers.
* The two integers represent the low bits Timing.clockTick0 and the high bits
* Timing.clockTickH0. When the low bit overflows to 0, the high bits increment.
*/
if (!(++stab_CL_20khz_M->Timing.clockTick0)) {
++stab_CL_20khz_M->Timing.clockTickH0;
}
stab_CL_20khz_M->Timing.taskTime0 = stab_CL_20khz_M->Timing.clockTick0 *
stab_CL_20khz_M->Timing.stepSize0 + stab_CL_20khz_M->Timing.clockTickH0 *
stab_CL_20khz_M->Timing.stepSize0 * 4294967296.0;
{
/* Base rate updates double buffers of absolute time for
asynchronous task. Double buffers are used to ensure
data integrity when asynchronous task reads absolute
time.
-- rtmL2HLastBufWr is the buffer index that is written last.
*/
boolean_T bufIdx = !stab_CL_20khz_M->Timing.rtmL2HLastBufWr;
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTick[bufIdx] =
stab_CL_20khz_M->Timing.clockTick0;
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTickH[bufIdx] =
stab_CL_20khz_M->Timing.clockTickH0;
stab_CL_20khz_M->Timing.rtmL2HLastBufWr = bufIdx;
}
}
/* Model initialize function */
void stab_CL_20khz_initialize(void)
{
/* Registration code */
/* initialize real-time model */
(void) memset((void *)stab_CL_20khz_M, 0,
sizeof(RT_MODEL_stab_CL_20khz_T));
rtmSetTFinal(stab_CL_20khz_M, -1);
stab_CL_20khz_M->Timing.stepSize0 = 0.2;
/* External mode info */
stab_CL_20khz_M->Sizes.checksums[0] = (313304726U);
stab_CL_20khz_M->Sizes.checksums[1] = (2234186893U);
stab_CL_20khz_M->Sizes.checksums[2] = (898971621U);
stab_CL_20khz_M->Sizes.checksums[3] = (485827866U);
{
static const sysRanDType rtAlwaysEnabled = SUBSYS_RAN_BC_ENABLE;
static RTWExtModeInfo rt_ExtModeInfo;
static const sysRanDType *systemRan[2];
stab_CL_20khz_M->extModeInfo = (&rt_ExtModeInfo);
rteiSetSubSystemActiveVectorAddresses(&rt_ExtModeInfo, systemRan);
systemRan[0] = &rtAlwaysEnabled;
systemRan[1] = (sysRanDType *)
&stab_CL_20khz_DW.PI_Controller_ISR_SubsysRanBC;
rteiSetModelMappingInfoPtr(stab_CL_20khz_M->extModeInfo,
&stab_CL_20khz_M->SpecialInfo.mappingInfo);
rteiSetChecksumsPtr(stab_CL_20khz_M->extModeInfo,
stab_CL_20khz_M->Sizes.checksums);
rteiSetTPtr(stab_CL_20khz_M->extModeInfo, rtmGetTPtr(stab_CL_20khz_M));
}
/* block I/O */
(void) memset(((void *) &stab_CL_20khz_B), 0,
sizeof(B_stab_CL_20khz_T));
/* states (dwork) */
(void) memset((void *)&stab_CL_20khz_DW, 0,
sizeof(DW_stab_CL_20khz_T));
/* data type transition information */
{
static DataTypeTransInfo dtInfo;
(void) memset((char_T *) &dtInfo, 0,
sizeof(dtInfo));
stab_CL_20khz_M->SpecialInfo.mappingInfo = (&dtInfo);
dtInfo.numDataTypes = 17;
dtInfo.dataTypeSizes = &rtDataTypeSizes[0];
dtInfo.dataTypeNames = &rtDataTypeNames[0];
/* Block I/O transition table */
dtInfo.BTransTable = &rtBTransTable;
}
/* SystemInitialize for S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' incorporates:
* SubSystem: '<Root>/PI_Controller_ISR'
*/
/* System initialize for function-call system: '<Root>/PI_Controller_ISR' */
/* Asynchronous task reads absolute time. Data (absolute time)
transfers from low priority task (base rate) to high priority
task (asynchronous rate). Double buffers are used to ensure
data integrity.
-- rtmL2HLastBufWr is the buffer index that is written last.
*/
stab_CL_20khz_M->Timing.clockTick1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTick
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
stab_CL_20khz_M->Timing.clockTickH1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTickH
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
/* Start for S-Function (c2802xpwm): '<S1>/ePWM_2' incorporates:
* Constant: '<S1>/Constant4'
*/
/*** Initialize ePWM2 modules ***/
{
/* // Time Base Control Register
EPwm2Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0; // Sync Output Select
EPwm2Regs.TBCTL.bit.PRDLD = 0; // Shadow select
EPwm2Regs.TBCTL2.bit.PRDLDSYNC = 0; // Shadow select
EPwm2Regs.TBCTL.bit.PHSEN = 1; // Phase Load Enable
EPwm2Regs.TBCTL.bit.PHSDIR = 0; // Phase Direction Bit
EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0; // High Speed TBCLK Pre-scaler
EPwm2Regs.TBCTL.bit.CLKDIV = 0; // Time Base Clock Pre-scaler
EPwm2Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
*/
EPwm2Regs.TBCTL.all = (EPwm2Regs.TBCTL.all & ~0x3FFF) | 0x4;
EPwm2Regs.TBCTL2.all = (EPwm2Regs.TBCTL2.all & ~0xC000) | 0x0;
/*-- Setup Time-Base (TB) Submodule --*/
EPwm2Regs.TBPRD = 10000; // Time Base Period Register
/* // Time-Base Phase Register
EPwm2Regs.TBPHS.bit.TBPHS = 0; // Phase offset register
*/
EPwm2Regs.TBPHS.all = (EPwm2Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
// Time Base Counter Register
EPwm2Regs.TBCTR = 0x0000; /* Clear counter*/
/*-- Setup Counter_Compare (CC) Submodule --*/
/* // Counter Compare Control Register
EPwm2Regs.CMPCTL.bit.LOADASYNC = 0U; // Active Compare A Load SYNC Option
EPwm2Regs.CMPCTL.bit.LOADBSYNC = 0U; // Active Compare B Load SYNC Option
EPwm2Regs.CMPCTL.bit.LOADAMODE = 1U; // Active Compare A Load
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0U; // Active Compare B Load
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0; // Compare A Register Block Operating Mode
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0; // Compare B Register Block Operating Mode
*/
EPwm2Regs.CMPCTL.all = (EPwm2Regs.CMPCTL.all & ~0x3C5F) | 0x1;
/* EPwm2Regs.CMPCTL2.bit.SHDWCMODE = 0; // Compare C Register Block Operating Mode
EPwm2Regs.CMPCTL2.bit.SHDWDMODE = 0; // Compare D Register Block Operating Mode
EPwm2Regs.CMPCTL2.bit.LOADCSYNC = 0U; // Active Compare C Load SYNC Option
EPwm2Regs.CMPCTL2.bit.LOADDSYNC = 0U; // Active Compare D Load SYNC Option
EPwm2Regs.CMPCTL2.bit.LOADCMODE = 0U; // Active Compare C Load
EPwm2Regs.CMPCTL2.bit.LOADDMODE = 0U; // Active Compare D Load
*/
EPwm2Regs.CMPCTL2.all = (EPwm2Regs.CMPCTL2.all & ~0x3C5F) | 0x0;
EPwm2Regs.CMPA.bit.CMPA = 5000; // Counter Compare A Register
EPwm2Regs.CMPB.bit.CMPB = 9862; // Counter Compare B Register
EPwm2Regs.CMPC = 32000; // Counter Compare C Register
EPwm2Regs.CMPD = 32000; // Counter Compare D Register
/*-- Setup Action-Qualifier (AQ) Submodule --*/
EPwm2Regs.AQCTLA.all = 146;// Action Qualifier Control Register For Output A
EPwm2Regs.AQCTLB.all = 2310;
// Action Qualifier Control Register For Output B
/* // Action Qualifier Software Force Register
EPwm2Regs.AQSFRC.bit.RLDCSF = 0; // Reload from Shadow Options
*/
EPwm2Regs.AQSFRC.all = (EPwm2Regs.AQSFRC.all & ~0xC0) | 0x0;
/* // Action Qualifier Continuous S/W Force Register
EPwm2Regs.AQCSFRC.bit.CSFA = 0; // Continuous Software Force on output A
EPwm2Regs.AQCSFRC.bit.CSFB = 0; // Continuous Software Force on output B
*/
EPwm2Regs.AQCSFRC.all = (EPwm2Regs.AQCSFRC.all & ~0xF) | 0x0;
/*-- Setup Dead-Band Generator (DB) Submodule --*/
/* // Dead-Band Generator Control Register
EPwm2Regs.DBCTL.bit.OUT_MODE = 3; // Dead Band Output Mode Control
EPwm2Regs.DBCTL.bit.IN_MODE = 0; // Dead Band Input Select Mode Control
EPwm2Regs.DBCTL.bit.POLSEL = 2; // Polarity Select Control
EPwm2Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable
EPwm2Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED shadow mode
EPwm2Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED shadow mode
EPwm2Regs.DBCTL.bit.LOADREDMODE = 4U; // DBRED load
EPwm2Regs.DBCTL.bit.LOADFEDMODE = 4U; // DBFED load
*/
EPwm2Regs.DBCTL.all = (EPwm2Regs.DBCTL.all & ~0x8FFF) | 0xB;
EPwm2Regs.DBRED.bit.DBRED = 20;
// Dead-Band Generator Rising Edge Delay Count Register
EPwm2Regs.DBFED.bit.DBFED = 20;
// Dead-Band Generator Falling Edge Delay Count Register
/*-- Setup Event-Trigger (ET) Submodule --*/
/* // Event Trigger Selection and Pre-Scale Register
EPwm2Regs.ETSEL.bit.SOCAEN = 0; // Start of Conversion A Enable
EPwm2Regs.ETSEL.bit.SOCASELCMP = 0;
EPwm2Regs.ETSEL.bit.SOCASEL = 2; // Start of Conversion A Select
EPwm2Regs.ETPS.bit.SOCPSSEL = 1; // EPWM2SOC Period Select
EPwm2Regs.ETSOCPS.bit.SOCAPRD2 = 1;
EPwm2Regs.ETSEL.bit.SOCBEN = 0; // Start of Conversion B Enable
EPwm2Regs.ETSEL.bit.SOCBSELCMP = 0;
EPwm2Regs.ETSEL.bit.SOCBSEL = 1; // Start of Conversion A Select
EPwm2Regs.ETPS.bit.SOCPSSEL = 1; // EPWM2SOCB Period Select
EPwm2Regs.ETSOCPS.bit.SOCBPRD2 = 1;
EPwm2Regs.ETSEL.bit.INTEN = 0; // EPWM2INTn Enable
EPwm2Regs.ETSEL.bit.INTSELCMP = 0;
EPwm2Regs.ETSEL.bit.INTSEL = 1; // Start of Conversion A Select
EPwm2Regs.ETPS.bit.INTPSSEL = 1; // EPWM2INTn Period Select
EPwm2Regs.ETINTPS.bit.INTPRD2 = 1;
*/
EPwm2Regs.ETSEL.all = (EPwm2Regs.ETSEL.all & ~0xFF7F) | 0x1201;
EPwm2Regs.ETPS.all = (EPwm2Regs.ETPS.all & ~0x30) | 0x30;
EPwm2Regs.ETSOCPS.all = (EPwm2Regs.ETSOCPS.all & ~0xF0F) | 0x101;
EPwm2Regs.ETINTPS.all = (EPwm2Regs.ETINTPS.all & ~0xF) | 0x1;
/*-- Setup PWM-Chopper (PC) Submodule --*/
/* // PWM Chopper Control Register
EPwm2Regs.PCCTL.bit.CHPEN = 0; // PWM chopping enable
EPwm2Regs.PCCTL.bit.CHPFREQ = 0; // Chopping clock frequency
EPwm2Regs.PCCTL.bit.OSHTWTH = 0; // One-shot pulse width
EPwm2Regs.PCCTL.bit.CHPDUTY = 0; // Chopping clock Duty cycle
*/
EPwm2Regs.PCCTL.all = (EPwm2Regs.PCCTL.all & ~0x7FF) | 0x0;
/*-- Set up Trip-Zone (TZ) Submodule --*/
EALLOW;
EPwm2Regs.TZSEL.all = 0; // Trip Zone Select Register
/* // Trip Zone Control Register
EPwm2Regs.TZCTL.bit.TZA = 3; // TZ1 to TZ6 Trip Action On EPWM2A
EPwm2Regs.TZCTL.bit.TZB = 3; // TZ1 to TZ6 Trip Action On EPWM2B
EPwm2Regs.TZCTL.bit.DCAEVT1 = 3; // EPWM2A action on DCAEVT1
EPwm2Regs.TZCTL.bit.DCAEVT2 = 3; // EPWM2A action on DCAEVT2
EPwm2Regs.TZCTL.bit.DCBEVT1 = 3; // EPWM2B action on DCBEVT1
EPwm2Regs.TZCTL.bit.DCBEVT2 = 3; // EPWM2B action on DCBEVT2
*/
EPwm2Regs.TZCTL.all = (EPwm2Regs.TZCTL.all & ~0xFFF) | 0xFFF;
/* // Trip Zone Enable Interrupt Register
EPwm2Regs.TZEINT.bit.OST = 0; // Trip Zones One Shot Int Enable
EPwm2Regs.TZEINT.bit.CBC = 0; // Trip Zones Cycle By Cycle Int Enable
EPwm2Regs.TZEINT.bit.DCAEVT1 = 0; // Digital Compare A Event 1 Int Enable
EPwm2Regs.TZEINT.bit.DCAEVT2 = 0; // Digital Compare A Event 2 Int Enable
EPwm2Regs.TZEINT.bit.DCBEVT1 = 0; // Digital Compare B Event 1 Int Enable
EPwm2Regs.TZEINT.bit.DCBEVT2 = 0; // Digital Compare B Event 2 Int Enable
*/
EPwm2Regs.TZEINT.all = (EPwm2Regs.TZEINT.all & ~0x7E) | 0x0;
/* // Digital Compare A Control Register
EPwm2Regs.DCACTL.bit.EVT1SYNCE = 0; // DCAEVT1 SYNC Enable
EPwm2Regs.DCACTL.bit.EVT1SOCE = 1; // DCAEVT1 SOC Enable
EPwm2Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal
EPwm2Regs.DCACTL.bit.EVT1SRCSEL = 0; // DCAEVT1 Source Signal
EPwm2Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal
EPwm2Regs.DCACTL.bit.EVT2SRCSEL = 0; // DCAEVT2 Source Signal
*/
EPwm2Regs.DCACTL.all = (EPwm2Regs.DCACTL.all & ~0x30F) | 0x4;
/* // Digital Compare B Control Register
EPwm2Regs.DCBCTL.bit.EVT1SYNCE = 0; // DCBEVT1 SYNC Enable
EPwm2Regs.DCBCTL.bit.EVT1SOCE = 0; // DCBEVT1 SOC Enable
EPwm2Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0; // DCBEVT1 Force Sync Signal
EPwm2Regs.DCBCTL.bit.EVT1SRCSEL = 0; // DCBEVT1 Source Signal
EPwm2Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0; // DCBEVT2 Force Sync Signal
EPwm2Regs.DCBCTL.bit.EVT2SRCSEL = 0; // DCBEVT2 Source Signal
*/
EPwm2Regs.DCBCTL.all = (EPwm2Regs.DCBCTL.all & ~0x30F) | 0x0;
/* // Digital Compare Trip Select Register
EPwm2Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0; // Digital Compare A High COMP Input Select
EPwm2Regs.DCTRIPSEL.bit.DCALCOMPSEL = 1; // Digital Compare A Low COMP Input Select
EPwm2Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0; // Digital Compare B High COMP Input Select
EPwm2Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 1; // Digital Compare B Low COMP Input Select
*/
EPwm2Regs.DCTRIPSEL.all = (EPwm2Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;
/* // Trip Zone Digital Comparator Select Register
EPwm2Regs.TZDCSEL.bit.DCAEVT1 = 0; // Digital Compare Output A Event 1
EPwm2Regs.TZDCSEL.bit.DCAEVT2 = 0; // Digital Compare Output A Event 2
EPwm2Regs.TZDCSEL.bit.DCBEVT1 = 0; // Digital Compare Output B Event 1
EPwm2Regs.TZDCSEL.bit.DCBEVT2 = 0; // Digital Compare Output B Event 2
*/
EPwm2Regs.TZDCSEL.all = (EPwm2Regs.TZDCSEL.all & ~0xFFF) | 0x0;
/* // Digital Compare Filter Control Register
EPwm2Regs.DCFCTL.bit.BLANKE = 0; // Blanking Enable/Disable
EPwm2Regs.DCFCTL.bit.PULSESEL = 1; // Pulse Select for Blanking & Capture Alignment
EPwm2Regs.DCFCTL.bit.BLANKINV = 0; // Blanking Window Inversion
EPwm2Regs.DCFCTL.bit.SRCSEL = 0; // Filter Block Signal Source Select
*/
EPwm2Regs.DCFCTL.all = (EPwm2Regs.DCFCTL.all & ~0x3F) | 0x10;
EPwm2Regs.DCFOFFSET = 0; // Digital Compare Filter Offset Register
EPwm2Regs.DCFWINDOW = 0; // Digital Compare Filter Window Register
/* // Digital Compare Capture Control Register
EPwm2Regs.DCCAPCTL.bit.CAPE = 0; // Counter Capture Enable
*/
EPwm2Regs.DCCAPCTL.all = (EPwm2Regs.DCCAPCTL.all & ~0x1) | 0x0;
/* // HRPWM Configuration Register
EPwm2Regs.HRCNFG.bit.SWAPAB = 0; // Swap EPWMA and EPWMB Outputs Bit
EPwm2Regs.HRCNFG.bit.SELOUTB = 0; // EPWMB Output Selection Bit
*/
EPwm2Regs.HRCNFG.all = (EPwm2Regs.HRCNFG.all & ~0xA0) | 0x0;
/* Update the Link Registers with the link value for all the Compare values and TBPRD */
/* No error is thrown if the ePWM register exists in the model or not */
EPwm2Regs.EPWMXLINK.bit.TBPRDLINK = 1;
EPwm2Regs.EPWMXLINK.bit.CMPALINK = 1;
EPwm2Regs.EPWMXLINK.bit.CMPBLINK = 1;
EPwm2Regs.EPWMXLINK.bit.CMPCLINK = 1;
EPwm2Regs.EPWMXLINK.bit.CMPDLINK = 1;
/* SYNCPER - Peripheral synchronization output event
EPwm2Regs.HRPCTL.bit.PWMSYNCSEL = 0; // EPWMSYNCPER selection
EPwm2Regs.HRPCTL.bit.PWMSYNCSELX = 0; // EPWMSYNCPER selection
*/
EPwm2Regs.HRPCTL.all = (EPwm2Regs.HRPCTL.all & ~0x72) | 0x0;
EDIS;
}
/* Start for S-Function (c2802xadc): '<S1>/Voltage Vout_FB' */
if (MW_adcCInitFlag == 0) {
InitAdcC();
MW_adcCInitFlag = 1;
}
config_ADCC_SOC0 ();
/* Start for S-Function (c2802xpwm): '<S1>/ePWM_3' */
/*** Initialize ePWM3 modules ***/
{
/* // Time Base Control Register
EPwm3Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0; // Sync Output Select
EPwm3Regs.TBCTL.bit.PRDLD = 0; // Shadow select
EPwm3Regs.TBCTL2.bit.PRDLDSYNC = 0; // Shadow select
EPwm3Regs.TBCTL.bit.PHSEN = 1; // Phase Load Enable
EPwm3Regs.TBCTL.bit.PHSDIR = 0; // Phase Direction Bit
EPwm3Regs.TBCTL.bit.HSPCLKDIV = 0; // High Speed TBCLK Pre-scaler
EPwm3Regs.TBCTL.bit.CLKDIV = 0; // Time Base Clock Pre-scaler
EPwm3Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
*/
EPwm3Regs.TBCTL.all = (EPwm3Regs.TBCTL.all & ~0x3FFF) | 0x4;
EPwm3Regs.TBCTL2.all = (EPwm3Regs.TBCTL2.all & ~0xC000) | 0x0;
/*-- Setup Time-Base (TB) Submodule --*/
EPwm3Regs.TBPRD = 10000; // Time Base Period Register
/* // Time-Base Phase Register
EPwm3Regs.TBPHS.bit.TBPHS = 0; // Phase offset register
*/
EPwm3Regs.TBPHS.all = (EPwm3Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
// Time Base Counter Register
EPwm3Regs.TBCTR = 0x0000; /* Clear counter*/
/*-- Setup Counter_Compare (CC) Submodule --*/
/* // Counter Compare Control Register
EPwm3Regs.CMPCTL.bit.LOADASYNC = 0U; // Active Compare A Load SYNC Option
EPwm3Regs.CMPCTL.bit.LOADBSYNC = 0U; // Active Compare B Load SYNC Option
EPwm3Regs.CMPCTL.bit.LOADAMODE = 1U; // Active Compare A Load
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0U; // Active Compare B Load
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0; // Compare A Register Block Operating Mode
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0; // Compare B Register Block Operating Mode
*/
EPwm3Regs.CMPCTL.all = (EPwm3Regs.CMPCTL.all & ~0x3C5F) | 0x1;
/* EPwm3Regs.CMPCTL2.bit.SHDWCMODE = 0; // Compare C Register Block Operating Mode
EPwm3Regs.CMPCTL2.bit.SHDWDMODE = 0; // Compare D Register Block Operating Mode
EPwm3Regs.CMPCTL2.bit.LOADCSYNC = 0U; // Active Compare C Load SYNC Option
EPwm3Regs.CMPCTL2.bit.LOADDSYNC = 0U; // Active Compare D Load SYNC Option
EPwm3Regs.CMPCTL2.bit.LOADCMODE = 0U; // Active Compare C Load
EPwm3Regs.CMPCTL2.bit.LOADDMODE = 0U; // Active Compare D Load
*/
EPwm3Regs.CMPCTL2.all = (EPwm3Regs.CMPCTL2.all & ~0x3C5F) | 0x0;
EPwm3Regs.CMPA.bit.CMPA = 5000; // Counter Compare A Register
EPwm3Regs.CMPB.bit.CMPB = 9862; // Counter Compare B Register
EPwm3Regs.CMPC = 32000; // Counter Compare C Register
EPwm3Regs.CMPD = 32000; // Counter Compare D Register
/*-- Setup Action-Qualifier (AQ) Submodule --*/
EPwm3Regs.AQCTLA.all = 146;// Action Qualifier Control Register For Output A
EPwm3Regs.AQCTLB.all = 2310;
// Action Qualifier Control Register For Output B
/* // Action Qualifier Software Force Register
EPwm3Regs.AQSFRC.bit.RLDCSF = 0; // Reload from Shadow Options
*/
EPwm3Regs.AQSFRC.all = (EPwm3Regs.AQSFRC.all & ~0xC0) | 0x0;
/* // Action Qualifier Continuous S/W Force Register
EPwm3Regs.AQCSFRC.bit.CSFA = 0; // Continuous Software Force on output A
EPwm3Regs.AQCSFRC.bit.CSFB = 0; // Continuous Software Force on output B
*/
EPwm3Regs.AQCSFRC.all = (EPwm3Regs.AQCSFRC.all & ~0xF) | 0x0;
/*-- Setup Dead-Band Generator (DB) Submodule --*/
/* // Dead-Band Generator Control Register
EPwm3Regs.DBCTL.bit.OUT_MODE = 3; // Dead Band Output Mode Control
EPwm3Regs.DBCTL.bit.IN_MODE = 0; // Dead Band Input Select Mode Control
EPwm3Regs.DBCTL.bit.POLSEL = 2; // Polarity Select Control
EPwm3Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable
EPwm3Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED shadow mode
EPwm3Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED shadow mode
EPwm3Regs.DBCTL.bit.LOADREDMODE = 4U; // DBRED load
EPwm3Regs.DBCTL.bit.LOADFEDMODE = 4U; // DBFED load
*/
EPwm3Regs.DBCTL.all = (EPwm3Regs.DBCTL.all & ~0x8FFF) | 0xB;
EPwm3Regs.DBRED.bit.DBRED = 20;
// Dead-Band Generator Rising Edge Delay Count Register
EPwm3Regs.DBFED.bit.DBFED = 20;
// Dead-Band Generator Falling Edge Delay Count Register
/*-- Setup Event-Trigger (ET) Submodule --*/
/* // Event Trigger Selection and Pre-Scale Register
EPwm3Regs.ETSEL.bit.SOCAEN = 0; // Start of Conversion A Enable
EPwm3Regs.ETSEL.bit.SOCASELCMP = 0;
EPwm3Regs.ETSEL.bit.SOCASEL = 2; // Start of Conversion A Select
EPwm3Regs.ETPS.bit.SOCPSSEL = 1; // EPWM3SOC Period Select
EPwm3Regs.ETSOCPS.bit.SOCAPRD2 = 1;
EPwm3Regs.ETSEL.bit.SOCBEN = 0; // Start of Conversion B Enable
EPwm3Regs.ETSEL.bit.SOCBSELCMP = 0;
EPwm3Regs.ETSEL.bit.SOCBSEL = 1; // Start of Conversion A Select
EPwm3Regs.ETPS.bit.SOCPSSEL = 1; // EPWM3SOCB Period Select
EPwm3Regs.ETSOCPS.bit.SOCBPRD2 = 1;
EPwm3Regs.ETSEL.bit.INTEN = 0; // EPWM3INTn Enable
EPwm3Regs.ETSEL.bit.INTSELCMP = 0;
EPwm3Regs.ETSEL.bit.INTSEL = 1; // Start of Conversion A Select
EPwm3Regs.ETPS.bit.INTPSSEL = 1; // EPWM3INTn Period Select
EPwm3Regs.ETINTPS.bit.INTPRD2 = 1;
*/
EPwm3Regs.ETSEL.all = (EPwm3Regs.ETSEL.all & ~0xFF7F) | 0x1201;
EPwm3Regs.ETPS.all = (EPwm3Regs.ETPS.all & ~0x30) | 0x30;
EPwm3Regs.ETSOCPS.all = (EPwm3Regs.ETSOCPS.all & ~0xF0F) | 0x101;
EPwm3Regs.ETINTPS.all = (EPwm3Regs.ETINTPS.all & ~0xF) | 0x1;
/*-- Setup PWM-Chopper (PC) Submodule --*/
/* // PWM Chopper Control Register
EPwm3Regs.PCCTL.bit.CHPEN = 0; // PWM chopping enable
EPwm3Regs.PCCTL.bit.CHPFREQ = 0; // Chopping clock frequency
EPwm3Regs.PCCTL.bit.OSHTWTH = 0; // One-shot pulse width
EPwm3Regs.PCCTL.bit.CHPDUTY = 0; // Chopping clock Duty cycle
*/
EPwm3Regs.PCCTL.all = (EPwm3Regs.PCCTL.all & ~0x7FF) | 0x0;
/*-- Set up Trip-Zone (TZ) Submodule --*/
EALLOW;
EPwm3Regs.TZSEL.all = 0; // Trip Zone Select Register
/* // Trip Zone Control Register
EPwm3Regs.TZCTL.bit.TZA = 3; // TZ1 to TZ6 Trip Action On EPWM3A
EPwm3Regs.TZCTL.bit.TZB = 3; // TZ1 to TZ6 Trip Action On EPWM3B
EPwm3Regs.TZCTL.bit.DCAEVT1 = 3; // EPWM3A action on DCAEVT1
EPwm3Regs.TZCTL.bit.DCAEVT2 = 3; // EPWM3A action on DCAEVT2
EPwm3Regs.TZCTL.bit.DCBEVT1 = 3; // EPWM3B action on DCBEVT1
EPwm3Regs.TZCTL.bit.DCBEVT2 = 3; // EPWM3B action on DCBEVT2
*/
EPwm3Regs.TZCTL.all = (EPwm3Regs.TZCTL.all & ~0xFFF) | 0xFFF;
/* // Trip Zone Enable Interrupt Register
EPwm3Regs.TZEINT.bit.OST = 0; // Trip Zones One Shot Int Enable
EPwm3Regs.TZEINT.bit.CBC = 0; // Trip Zones Cycle By Cycle Int Enable
EPwm3Regs.TZEINT.bit.DCAEVT1 = 0; // Digital Compare A Event 1 Int Enable
EPwm3Regs.TZEINT.bit.DCAEVT2 = 0; // Digital Compare A Event 2 Int Enable
EPwm3Regs.TZEINT.bit.DCBEVT1 = 0; // Digital Compare B Event 1 Int Enable
EPwm3Regs.TZEINT.bit.DCBEVT2 = 0; // Digital Compare B Event 2 Int Enable
*/
EPwm3Regs.TZEINT.all = (EPwm3Regs.TZEINT.all & ~0x7E) | 0x0;
/* // Digital Compare A Control Register
EPwm3Regs.DCACTL.bit.EVT1SYNCE = 0; // DCAEVT1 SYNC Enable
EPwm3Regs.DCACTL.bit.EVT1SOCE = 1; // DCAEVT1 SOC Enable
EPwm3Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal
EPwm3Regs.DCACTL.bit.EVT1SRCSEL = 0; // DCAEVT1 Source Signal
EPwm3Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal
EPwm3Regs.DCACTL.bit.EVT2SRCSEL = 0; // DCAEVT2 Source Signal
*/
EPwm3Regs.DCACTL.all = (EPwm3Regs.DCACTL.all & ~0x30F) | 0x4;
/* // Digital Compare B Control Register
EPwm3Regs.DCBCTL.bit.EVT1SYNCE = 0; // DCBEVT1 SYNC Enable
EPwm3Regs.DCBCTL.bit.EVT1SOCE = 0; // DCBEVT1 SOC Enable
EPwm3Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0; // DCBEVT1 Force Sync Signal
EPwm3Regs.DCBCTL.bit.EVT1SRCSEL = 0; // DCBEVT1 Source Signal
EPwm3Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0; // DCBEVT2 Force Sync Signal
EPwm3Regs.DCBCTL.bit.EVT2SRCSEL = 0; // DCBEVT2 Source Signal
*/
EPwm3Regs.DCBCTL.all = (EPwm3Regs.DCBCTL.all & ~0x30F) | 0x0;
/* // Digital Compare Trip Select Register
EPwm3Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0; // Digital Compare A High COMP Input Select
EPwm3Regs.DCTRIPSEL.bit.DCALCOMPSEL = 1; // Digital Compare A Low COMP Input Select
EPwm3Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0; // Digital Compare B High COMP Input Select
EPwm3Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 1; // Digital Compare B Low COMP Input Select
*/
EPwm3Regs.DCTRIPSEL.all = (EPwm3Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;
/* // Trip Zone Digital Comparator Select Register
EPwm3Regs.TZDCSEL.bit.DCAEVT1 = 0; // Digital Compare Output A Event 1
EPwm3Regs.TZDCSEL.bit.DCAEVT2 = 0; // Digital Compare Output A Event 2
EPwm3Regs.TZDCSEL.bit.DCBEVT1 = 0; // Digital Compare Output B Event 1
EPwm3Regs.TZDCSEL.bit.DCBEVT2 = 0; // Digital Compare Output B Event 2
*/
EPwm3Regs.TZDCSEL.all = (EPwm3Regs.TZDCSEL.all & ~0xFFF) | 0x0;
/* // Digital Compare Filter Control Register
EPwm3Regs.DCFCTL.bit.BLANKE = 0; // Blanking Enable/Disable
EPwm3Regs.DCFCTL.bit.PULSESEL = 1; // Pulse Select for Blanking & Capture Alignment
EPwm3Regs.DCFCTL.bit.BLANKINV = 0; // Blanking Window Inversion
EPwm3Regs.DCFCTL.bit.SRCSEL = 0; // Filter Block Signal Source Select
*/
EPwm3Regs.DCFCTL.all = (EPwm3Regs.DCFCTL.all & ~0x3F) | 0x10;
EPwm3Regs.DCFOFFSET = 0; // Digital Compare Filter Offset Register
EPwm3Regs.DCFWINDOW = 0; // Digital Compare Filter Window Register
/* // Digital Compare Capture Control Register
EPwm3Regs.DCCAPCTL.bit.CAPE = 0; // Counter Capture Enable
*/
EPwm3Regs.DCCAPCTL.all = (EPwm3Regs.DCCAPCTL.all & ~0x1) | 0x0;
/* // HRPWM Configuration Register
EPwm3Regs.HRCNFG.bit.SWAPAB = 0; // Swap EPWMA and EPWMB Outputs Bit
EPwm3Regs.HRCNFG.bit.SELOUTB = 0; // EPWMB Output Selection Bit
*/
EPwm3Regs.HRCNFG.all = (EPwm3Regs.HRCNFG.all & ~0xA0) | 0x0;
/* Update the Link Registers with the link value for all the Compare values and TBPRD */
/* No error is thrown if the ePWM register exists in the model or not */
EPwm3Regs.EPWMXLINK.bit.TBPRDLINK = 2;
EPwm3Regs.EPWMXLINK.bit.CMPALINK = 2;
EPwm3Regs.EPWMXLINK.bit.CMPBLINK = 2;
EPwm3Regs.EPWMXLINK.bit.CMPCLINK = 2;
EPwm3Regs.EPWMXLINK.bit.CMPDLINK = 2;
/* SYNCPER - Peripheral synchronization output event
EPwm3Regs.HRPCTL.bit.PWMSYNCSEL = 0; // EPWMSYNCPER selection
EPwm3Regs.HRPCTL.bit.PWMSYNCSELX = 0; // EPWMSYNCPER selection
*/
EPwm3Regs.HRPCTL.all = (EPwm3Regs.HRPCTL.all & ~0x72) | 0x0;
EDIS;
}
/* Start for S-Function (c2802xpwm): '<S1>/ePWM_4' */
/*** Initialize ePWM4 modules ***/
{
/* // Time Base Control Register
EPwm4Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0; // Sync Output Select
EPwm4Regs.TBCTL.bit.PRDLD = 0; // Shadow select
EPwm4Regs.TBCTL2.bit.PRDLDSYNC = 0; // Shadow select
EPwm4Regs.TBCTL.bit.PHSEN = 1; // Phase Load Enable
EPwm4Regs.TBCTL.bit.PHSDIR = 0; // Phase Direction Bit
EPwm4Regs.TBCTL.bit.HSPCLKDIV = 0; // High Speed TBCLK Pre-scaler
EPwm4Regs.TBCTL.bit.CLKDIV = 0; // Time Base Clock Pre-scaler
EPwm4Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
*/
EPwm4Regs.TBCTL.all = (EPwm4Regs.TBCTL.all & ~0x3FFF) | 0x4;
EPwm4Regs.TBCTL2.all = (EPwm4Regs.TBCTL2.all & ~0xC000) | 0x0;
/*-- Setup Time-Base (TB) Submodule --*/
EPwm4Regs.TBPRD = 10000; // Time Base Period Register
/* // Time-Base Phase Register
EPwm4Regs.TBPHS.bit.TBPHS = 0; // Phase offset register
*/
EPwm4Regs.TBPHS.all = (EPwm4Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
// Time Base Counter Register
EPwm4Regs.TBCTR = 0x0000; /* Clear counter*/
/*-- Setup Counter_Compare (CC) Submodule --*/
/* // Counter Compare Control Register
EPwm4Regs.CMPCTL.bit.LOADASYNC = 0U; // Active Compare A Load SYNC Option
EPwm4Regs.CMPCTL.bit.LOADBSYNC = 0U; // Active Compare B Load SYNC Option
EPwm4Regs.CMPCTL.bit.LOADAMODE = 1U; // Active Compare A Load
EPwm4Regs.CMPCTL.bit.LOADBMODE = 0U; // Active Compare B Load
EPwm4Regs.CMPCTL.bit.SHDWAMODE = 0; // Compare A Register Block Operating Mode
EPwm4Regs.CMPCTL.bit.SHDWBMODE = 0; // Compare B Register Block Operating Mode
*/
EPwm4Regs.CMPCTL.all = (EPwm4Regs.CMPCTL.all & ~0x3C5F) | 0x1;
/* EPwm4Regs.CMPCTL2.bit.SHDWCMODE = 0; // Compare C Register Block Operating Mode
EPwm4Regs.CMPCTL2.bit.SHDWDMODE = 0; // Compare D Register Block Operating Mode
EPwm4Regs.CMPCTL2.bit.LOADCSYNC = 0U; // Active Compare C Load SYNC Option
EPwm4Regs.CMPCTL2.bit.LOADDSYNC = 0U; // Active Compare D Load SYNC Option
EPwm4Regs.CMPCTL2.bit.LOADCMODE = 0U; // Active Compare C Load
EPwm4Regs.CMPCTL2.bit.LOADDMODE = 0U; // Active Compare D Load
*/
EPwm4Regs.CMPCTL2.all = (EPwm4Regs.CMPCTL2.all & ~0x3C5F) | 0x0;
EPwm4Regs.CMPA.bit.CMPA = 5000; // Counter Compare A Register
EPwm4Regs.CMPB.bit.CMPB = 9862; // Counter Compare B Register
EPwm4Regs.CMPC = 32000; // Counter Compare C Register
EPwm4Regs.CMPD = 32000; // Counter Compare D Register
/*-- Setup Action-Qualifier (AQ) Submodule --*/
EPwm4Regs.AQCTLA.all = 146;// Action Qualifier Control Register For Output A
EPwm4Regs.AQCTLB.all = 2310;
// Action Qualifier Control Register For Output B
/* // Action Qualifier Software Force Register
EPwm4Regs.AQSFRC.bit.RLDCSF = 0; // Reload from Shadow Options
*/
EPwm4Regs.AQSFRC.all = (EPwm4Regs.AQSFRC.all & ~0xC0) | 0x0;
/* // Action Qualifier Continuous S/W Force Register
EPwm4Regs.AQCSFRC.bit.CSFA = 0; // Continuous Software Force on output A
EPwm4Regs.AQCSFRC.bit.CSFB = 0; // Continuous Software Force on output B
*/
EPwm4Regs.AQCSFRC.all = (EPwm4Regs.AQCSFRC.all & ~0xF) | 0x0;
/*-- Setup Dead-Band Generator (DB) Submodule --*/
/* // Dead-Band Generator Control Register
EPwm4Regs.DBCTL.bit.OUT_MODE = 3; // Dead Band Output Mode Control
EPwm4Regs.DBCTL.bit.IN_MODE = 0; // Dead Band Input Select Mode Control
EPwm4Regs.DBCTL.bit.POLSEL = 2; // Polarity Select Control
EPwm4Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable
EPwm4Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED shadow mode
EPwm4Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED shadow mode
EPwm4Regs.DBCTL.bit.LOADREDMODE = 4U; // DBRED load
EPwm4Regs.DBCTL.bit.LOADFEDMODE = 4U; // DBFED load
*/
EPwm4Regs.DBCTL.all = (EPwm4Regs.DBCTL.all & ~0x8FFF) | 0xB;
EPwm4Regs.DBRED.bit.DBRED = 20;
// Dead-Band Generator Rising Edge Delay Count Register
EPwm4Regs.DBFED.bit.DBFED = 20;
// Dead-Band Generator Falling Edge Delay Count Register
/*-- Setup Event-Trigger (ET) Submodule --*/
/* // Event Trigger Selection and Pre-Scale Register
EPwm4Regs.ETSEL.bit.SOCAEN = 0; // Start of Conversion A Enable
EPwm4Regs.ETSEL.bit.SOCASELCMP = 0;
EPwm4Regs.ETSEL.bit.SOCASEL = 2; // Start of Conversion A Select
EPwm4Regs.ETPS.bit.SOCPSSEL = 1; // EPWM4SOC Period Select
EPwm4Regs.ETSOCPS.bit.SOCAPRD2 = 1;
EPwm4Regs.ETSEL.bit.SOCBEN = 0; // Start of Conversion B Enable
EPwm4Regs.ETSEL.bit.SOCBSELCMP = 0;
EPwm4Regs.ETSEL.bit.SOCBSEL = 1; // Start of Conversion A Select
EPwm4Regs.ETPS.bit.SOCPSSEL = 1; // EPWM4SOCB Period Select
EPwm4Regs.ETSOCPS.bit.SOCBPRD2 = 1;
EPwm4Regs.ETSEL.bit.INTEN = 0; // EPWM4INTn Enable
EPwm4Regs.ETSEL.bit.INTSELCMP = 0;
EPwm4Regs.ETSEL.bit.INTSEL = 1; // Start of Conversion A Select
EPwm4Regs.ETPS.bit.INTPSSEL = 1; // EPWM4INTn Period Select
EPwm4Regs.ETINTPS.bit.INTPRD2 = 1;
*/
EPwm4Regs.ETSEL.all = (EPwm4Regs.ETSEL.all & ~0xFF7F) | 0x1201;
EPwm4Regs.ETPS.all = (EPwm4Regs.ETPS.all & ~0x30) | 0x30;
EPwm4Regs.ETSOCPS.all = (EPwm4Regs.ETSOCPS.all & ~0xF0F) | 0x101;
EPwm4Regs.ETINTPS.all = (EPwm4Regs.ETINTPS.all & ~0xF) | 0x1;
/*-- Setup PWM-Chopper (PC) Submodule --*/
/* // PWM Chopper Control Register
EPwm4Regs.PCCTL.bit.CHPEN = 0; // PWM chopping enable
EPwm4Regs.PCCTL.bit.CHPFREQ = 0; // Chopping clock frequency
EPwm4Regs.PCCTL.bit.OSHTWTH = 0; // One-shot pulse width
EPwm4Regs.PCCTL.bit.CHPDUTY = 0; // Chopping clock Duty cycle
*/
EPwm4Regs.PCCTL.all = (EPwm4Regs.PCCTL.all & ~0x7FF) | 0x0;
/*-- Set up Trip-Zone (TZ) Submodule --*/
EALLOW;
EPwm4Regs.TZSEL.all = 0; // Trip Zone Select Register
/* // Trip Zone Control Register
EPwm4Regs.TZCTL.bit.TZA = 3; // TZ1 to TZ6 Trip Action On EPWM4A
EPwm4Regs.TZCTL.bit.TZB = 3; // TZ1 to TZ6 Trip Action On EPWM4B
EPwm4Regs.TZCTL.bit.DCAEVT1 = 3; // EPWM4A action on DCAEVT1
EPwm4Regs.TZCTL.bit.DCAEVT2 = 3; // EPWM4A action on DCAEVT2
EPwm4Regs.TZCTL.bit.DCBEVT1 = 3; // EPWM4B action on DCBEVT1
EPwm4Regs.TZCTL.bit.DCBEVT2 = 3; // EPWM4B action on DCBEVT2
*/
EPwm4Regs.TZCTL.all = (EPwm4Regs.TZCTL.all & ~0xFFF) | 0xFFF;
/* // Trip Zone Enable Interrupt Register
EPwm4Regs.TZEINT.bit.OST = 0; // Trip Zones One Shot Int Enable
EPwm4Regs.TZEINT.bit.CBC = 0; // Trip Zones Cycle By Cycle Int Enable
EPwm4Regs.TZEINT.bit.DCAEVT1 = 0; // Digital Compare A Event 1 Int Enable
EPwm4Regs.TZEINT.bit.DCAEVT2 = 0; // Digital Compare A Event 2 Int Enable
EPwm4Regs.TZEINT.bit.DCBEVT1 = 0; // Digital Compare B Event 1 Int Enable
EPwm4Regs.TZEINT.bit.DCBEVT2 = 0; // Digital Compare B Event 2 Int Enable
*/
EPwm4Regs.TZEINT.all = (EPwm4Regs.TZEINT.all & ~0x7E) | 0x0;
/* // Digital Compare A Control Register
EPwm4Regs.DCACTL.bit.EVT1SYNCE = 0; // DCAEVT1 SYNC Enable
EPwm4Regs.DCACTL.bit.EVT1SOCE = 1; // DCAEVT1 SOC Enable
EPwm4Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal
EPwm4Regs.DCACTL.bit.EVT1SRCSEL = 0; // DCAEVT1 Source Signal
EPwm4Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal
EPwm4Regs.DCACTL.bit.EVT2SRCSEL = 0; // DCAEVT2 Source Signal
*/
EPwm4Regs.DCACTL.all = (EPwm4Regs.DCACTL.all & ~0x30F) | 0x4;
/* // Digital Compare B Control Register
EPwm4Regs.DCBCTL.bit.EVT1SYNCE = 0; // DCBEVT1 SYNC Enable
EPwm4Regs.DCBCTL.bit.EVT1SOCE = 0; // DCBEVT1 SOC Enable
EPwm4Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0; // DCBEVT1 Force Sync Signal
EPwm4Regs.DCBCTL.bit.EVT1SRCSEL = 0; // DCBEVT1 Source Signal
EPwm4Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0; // DCBEVT2 Force Sync Signal
EPwm4Regs.DCBCTL.bit.EVT2SRCSEL = 0; // DCBEVT2 Source Signal
*/
EPwm4Regs.DCBCTL.all = (EPwm4Regs.DCBCTL.all & ~0x30F) | 0x0;
/* // Digital Compare Trip Select Register
EPwm4Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0; // Digital Compare A High COMP Input Select
EPwm4Regs.DCTRIPSEL.bit.DCALCOMPSEL = 1; // Digital Compare A Low COMP Input Select
EPwm4Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0; // Digital Compare B High COMP Input Select
EPwm4Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 1; // Digital Compare B Low COMP Input Select
*/
EPwm4Regs.DCTRIPSEL.all = (EPwm4Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;
/* // Trip Zone Digital Comparator Select Register
EPwm4Regs.TZDCSEL.bit.DCAEVT1 = 0; // Digital Compare Output A Event 1
EPwm4Regs.TZDCSEL.bit.DCAEVT2 = 0; // Digital Compare Output A Event 2
EPwm4Regs.TZDCSEL.bit.DCBEVT1 = 0; // Digital Compare Output B Event 1
EPwm4Regs.TZDCSEL.bit.DCBEVT2 = 0; // Digital Compare Output B Event 2
*/
EPwm4Regs.TZDCSEL.all = (EPwm4Regs.TZDCSEL.all & ~0xFFF) | 0x0;
/* // Digital Compare Filter Control Register
EPwm4Regs.DCFCTL.bit.BLANKE = 0; // Blanking Enable/Disable
EPwm4Regs.DCFCTL.bit.PULSESEL = 1; // Pulse Select for Blanking & Capture Alignment
EPwm4Regs.DCFCTL.bit.BLANKINV = 0; // Blanking Window Inversion
EPwm4Regs.DCFCTL.bit.SRCSEL = 0; // Filter Block Signal Source Select
*/
EPwm4Regs.DCFCTL.all = (EPwm4Regs.DCFCTL.all & ~0x3F) | 0x10;
EPwm4Regs.DCFOFFSET = 0; // Digital Compare Filter Offset Register
EPwm4Regs.DCFWINDOW = 0; // Digital Compare Filter Window Register
/* // Digital Compare Capture Control Register
EPwm4Regs.DCCAPCTL.bit.CAPE = 0; // Counter Capture Enable
*/
EPwm4Regs.DCCAPCTL.all = (EPwm4Regs.DCCAPCTL.all & ~0x1) | 0x0;
/* // HRPWM Configuration Register
EPwm4Regs.HRCNFG.bit.SWAPAB = 0; // Swap EPWMA and EPWMB Outputs Bit
EPwm4Regs.HRCNFG.bit.SELOUTB = 0; // EPWMB Output Selection Bit
*/
EPwm4Regs.HRCNFG.all = (EPwm4Regs.HRCNFG.all & ~0xA0) | 0x0;
/* Update the Link Registers with the link value for all the Compare values and TBPRD */
/* No error is thrown if the ePWM register exists in the model or not */
EPwm4Regs.EPWMXLINK.bit.TBPRDLINK = 3;
EPwm4Regs.EPWMXLINK.bit.CMPALINK = 3;
EPwm4Regs.EPWMXLINK.bit.CMPBLINK = 3;
EPwm4Regs.EPWMXLINK.bit.CMPCLINK = 3;
EPwm4Regs.EPWMXLINK.bit.CMPDLINK = 3;
/* SYNCPER - Peripheral synchronization output event
EPwm4Regs.HRPCTL.bit.PWMSYNCSEL = 0; // EPWMSYNCPER selection
EPwm4Regs.HRPCTL.bit.PWMSYNCSELX = 0; // EPWMSYNCPER selection
*/
EPwm4Regs.HRPCTL.all = (EPwm4Regs.HRPCTL.all & ~0x72) | 0x0;
EDIS;
}
/* Start for S-Function (c2802xpwm): '<S1>/ePWM_1' */
/*** Initialize ePWM1 modules ***/
{
/* // Time Base Control Register
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Counter Mode
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // Sync Output Select
EPwm1Regs.TBCTL.bit.PRDLD = 0; // Shadow select
EPwm1Regs.TBCTL2.bit.PRDLDSYNC = 0; // Shadow select
EPwm1Regs.TBCTL.bit.PHSEN = 0; // Phase Load Enable
EPwm1Regs.TBCTL.bit.PHSDIR = 0; // Phase Direction Bit
EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0; // High Speed TBCLK Pre-scaler
EPwm1Regs.TBCTL.bit.CLKDIV = 0; // Time Base Clock Pre-scaler
EPwm1Regs.TBCTL.bit.SWFSYNC = 0; // Software Force Sync Pulse
*/
EPwm1Regs.TBCTL.all = (EPwm1Regs.TBCTL.all & ~0x3FFF) | 0x10;
EPwm1Regs.TBCTL2.all = (EPwm1Regs.TBCTL2.all & ~0xC000) | 0x0;
/*-- Setup Time-Base (TB) Submodule --*/
EPwm1Regs.TBPRD = 10000; // Time Base Period Register
/* // Time-Base Phase Register
EPwm1Regs.TBPHS.bit.TBPHS = 0; // Phase offset register
*/
EPwm1Regs.TBPHS.all = (EPwm1Regs.TBPHS.all & ~0xFFFF0000) | 0x0;
// Time Base Counter Register
EPwm1Regs.TBCTR = 0x0000; /* Clear counter*/
/*-- Setup Counter_Compare (CC) Submodule --*/
/* // Counter Compare Control Register
EPwm1Regs.CMPCTL.bit.LOADASYNC = 0U; // Active Compare A Load SYNC Option
EPwm1Regs.CMPCTL.bit.LOADBSYNC = 0U; // Active Compare B Load SYNC Option
EPwm1Regs.CMPCTL.bit.LOADAMODE = 1U; // Active Compare A Load
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0U; // Active Compare B Load
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0; // Compare A Register Block Operating Mode
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0; // Compare B Register Block Operating Mode
*/
EPwm1Regs.CMPCTL.all = (EPwm1Regs.CMPCTL.all & ~0x3C5F) | 0x1;
/* EPwm1Regs.CMPCTL2.bit.SHDWCMODE = 0; // Compare C Register Block Operating Mode
EPwm1Regs.CMPCTL2.bit.SHDWDMODE = 0; // Compare D Register Block Operating Mode
EPwm1Regs.CMPCTL2.bit.LOADCSYNC = 0U; // Active Compare C Load SYNC Option
EPwm1Regs.CMPCTL2.bit.LOADDSYNC = 0U; // Active Compare D Load SYNC Option
EPwm1Regs.CMPCTL2.bit.LOADCMODE = 0U; // Active Compare C Load
EPwm1Regs.CMPCTL2.bit.LOADDMODE = 0U; // Active Compare D Load
*/
EPwm1Regs.CMPCTL2.all = (EPwm1Regs.CMPCTL2.all & ~0x3C5F) | 0x0;
EPwm1Regs.CMPA.bit.CMPA = 5000; // Counter Compare A Register
EPwm1Regs.CMPB.bit.CMPB = 9862; // Counter Compare B Register
EPwm1Regs.CMPC = 32000; // Counter Compare C Register
EPwm1Regs.CMPD = 32000; // Counter Compare D Register
/*-- Setup Action-Qualifier (AQ) Submodule --*/
EPwm1Regs.AQCTLA.all = 146;// Action Qualifier Control Register For Output A
EPwm1Regs.AQCTLB.all = 2310;
// Action Qualifier Control Register For Output B
/* // Action Qualifier Software Force Register
EPwm1Regs.AQSFRC.bit.RLDCSF = 0; // Reload from Shadow Options
*/
EPwm1Regs.AQSFRC.all = (EPwm1Regs.AQSFRC.all & ~0xC0) | 0x0;
/* // Action Qualifier Continuous S/W Force Register
EPwm1Regs.AQCSFRC.bit.CSFA = 0; // Continuous Software Force on output A
EPwm1Regs.AQCSFRC.bit.CSFB = 0; // Continuous Software Force on output B
*/
EPwm1Regs.AQCSFRC.all = (EPwm1Regs.AQCSFRC.all & ~0xF) | 0x0;
/*-- Setup Dead-Band Generator (DB) Submodule --*/
/* // Dead-Band Generator Control Register
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // Dead Band Output Mode Control
EPwm1Regs.DBCTL.bit.IN_MODE = 0; // Dead Band Input Select Mode Control
EPwm1Regs.DBCTL.bit.POLSEL = 2; // Polarity Select Control
EPwm1Regs.DBCTL.bit.HALFCYCLE = 0; // Half Cycle Clocking Enable
EPwm1Regs.DBCTL.bit.SHDWDBREDMODE = 0; // DBRED shadow mode
EPwm1Regs.DBCTL.bit.SHDWDBFEDMODE = 0; // DBFED shadow mode
EPwm1Regs.DBCTL.bit.LOADREDMODE = 4U; // DBRED load
EPwm1Regs.DBCTL.bit.LOADFEDMODE = 4U; // DBFED load
*/
EPwm1Regs.DBCTL.all = (EPwm1Regs.DBCTL.all & ~0x8FFF) | 0xB;
EPwm1Regs.DBRED.bit.DBRED = 20;
// Dead-Band Generator Rising Edge Delay Count Register
EPwm1Regs.DBFED.bit.DBFED = 20;
// Dead-Band Generator Falling Edge Delay Count Register
/*-- Setup Event-Trigger (ET) Submodule --*/
/* // Event Trigger Selection and Pre-Scale Register
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Start of Conversion A Enable
EPwm1Regs.ETSEL.bit.SOCASELCMP = 0;
EPwm1Regs.ETSEL.bit.SOCASEL = 6; // Start of Conversion A Select
EPwm1Regs.ETPS.bit.SOCPSSEL = 1; // EPWM1SOC Period Select
EPwm1Regs.ETSOCPS.bit.SOCAPRD2 = 1;
EPwm1Regs.ETSEL.bit.SOCBEN = 0; // Start of Conversion B Enable
EPwm1Regs.ETSEL.bit.SOCBSELCMP = 0;
EPwm1Regs.ETSEL.bit.SOCBSEL = 1; // Start of Conversion A Select
EPwm1Regs.ETPS.bit.SOCPSSEL = 1; // EPWM1SOCB Period Select
EPwm1Regs.ETSOCPS.bit.SOCBPRD2 = 1;
EPwm1Regs.ETSEL.bit.INTEN = 0; // EPWM1INTn Enable
EPwm1Regs.ETSEL.bit.INTSELCMP = 0;
EPwm1Regs.ETSEL.bit.INTSEL = 1; // Start of Conversion A Select
EPwm1Regs.ETPS.bit.INTPSSEL = 1; // EPWM1INTn Period Select
EPwm1Regs.ETINTPS.bit.INTPRD2 = 1;
*/
EPwm1Regs.ETSEL.all = (EPwm1Regs.ETSEL.all & ~0xFF7F) | 0x1E01;
EPwm1Regs.ETPS.all = (EPwm1Regs.ETPS.all & ~0x30) | 0x30;
EPwm1Regs.ETSOCPS.all = (EPwm1Regs.ETSOCPS.all & ~0xF0F) | 0x101;
EPwm1Regs.ETINTPS.all = (EPwm1Regs.ETINTPS.all & ~0xF) | 0x1;
/*-- Setup PWM-Chopper (PC) Submodule --*/
/* // PWM Chopper Control Register
EPwm1Regs.PCCTL.bit.CHPEN = 0; // PWM chopping enable
EPwm1Regs.PCCTL.bit.CHPFREQ = 0; // Chopping clock frequency
EPwm1Regs.PCCTL.bit.OSHTWTH = 0; // One-shot pulse width
EPwm1Regs.PCCTL.bit.CHPDUTY = 0; // Chopping clock Duty cycle
*/
EPwm1Regs.PCCTL.all = (EPwm1Regs.PCCTL.all & ~0x7FF) | 0x0;
/*-- Set up Trip-Zone (TZ) Submodule --*/
EALLOW;
EPwm1Regs.TZSEL.all = 0; // Trip Zone Select Register
/* // Trip Zone Control Register
EPwm1Regs.TZCTL.bit.TZA = 3; // TZ1 to TZ6 Trip Action On EPWM1A
EPwm1Regs.TZCTL.bit.TZB = 3; // TZ1 to TZ6 Trip Action On EPWM1B
EPwm1Regs.TZCTL.bit.DCAEVT1 = 3; // EPWM1A action on DCAEVT1
EPwm1Regs.TZCTL.bit.DCAEVT2 = 3; // EPWM1A action on DCAEVT2
EPwm1Regs.TZCTL.bit.DCBEVT1 = 3; // EPWM1B action on DCBEVT1
EPwm1Regs.TZCTL.bit.DCBEVT2 = 3; // EPWM1B action on DCBEVT2
*/
EPwm1Regs.TZCTL.all = (EPwm1Regs.TZCTL.all & ~0xFFF) | 0xFFF;
/* // Trip Zone Enable Interrupt Register
EPwm1Regs.TZEINT.bit.OST = 0; // Trip Zones One Shot Int Enable
EPwm1Regs.TZEINT.bit.CBC = 0; // Trip Zones Cycle By Cycle Int Enable
EPwm1Regs.TZEINT.bit.DCAEVT1 = 0; // Digital Compare A Event 1 Int Enable
EPwm1Regs.TZEINT.bit.DCAEVT2 = 0; // Digital Compare A Event 2 Int Enable
EPwm1Regs.TZEINT.bit.DCBEVT1 = 0; // Digital Compare B Event 1 Int Enable
EPwm1Regs.TZEINT.bit.DCBEVT2 = 0; // Digital Compare B Event 2 Int Enable
*/
EPwm1Regs.TZEINT.all = (EPwm1Regs.TZEINT.all & ~0x7E) | 0x0;
/* // Digital Compare A Control Register
EPwm1Regs.DCACTL.bit.EVT1SYNCE = 0; // DCAEVT1 SYNC Enable
EPwm1Regs.DCACTL.bit.EVT1SOCE = 1; // DCAEVT1 SOC Enable
EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = 0; // DCAEVT1 Force Sync Signal
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 0; // DCAEVT1 Source Signal
EPwm1Regs.DCACTL.bit.EVT2FRCSYNCSEL = 0; // DCAEVT2 Force Sync Signal
EPwm1Regs.DCACTL.bit.EVT2SRCSEL = 0; // DCAEVT2 Source Signal
*/
EPwm1Regs.DCACTL.all = (EPwm1Regs.DCACTL.all & ~0x30F) | 0x4;
/* // Digital Compare B Control Register
EPwm1Regs.DCBCTL.bit.EVT1SYNCE = 0; // DCBEVT1 SYNC Enable
EPwm1Regs.DCBCTL.bit.EVT1SOCE = 0; // DCBEVT1 SOC Enable
EPwm1Regs.DCBCTL.bit.EVT1FRCSYNCSEL = 0; // DCBEVT1 Force Sync Signal
EPwm1Regs.DCBCTL.bit.EVT1SRCSEL = 0; // DCBEVT1 Source Signal
EPwm1Regs.DCBCTL.bit.EVT2FRCSYNCSEL = 0; // DCBEVT2 Force Sync Signal
EPwm1Regs.DCBCTL.bit.EVT2SRCSEL = 0; // DCBEVT2 Source Signal
*/
EPwm1Regs.DCBCTL.all = (EPwm1Regs.DCBCTL.all & ~0x30F) | 0x0;
/* // Digital Compare Trip Select Register
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 0; // Digital Compare A High COMP Input Select
EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = 1; // Digital Compare A Low COMP Input Select
EPwm1Regs.DCTRIPSEL.bit.DCBHCOMPSEL = 0; // Digital Compare B High COMP Input Select
EPwm1Regs.DCTRIPSEL.bit.DCBLCOMPSEL = 1; // Digital Compare B Low COMP Input Select
*/
EPwm1Regs.DCTRIPSEL.all = (EPwm1Regs.DCTRIPSEL.all & ~ 0xFFFF) | 0x1010;
/* // Trip Zone Digital Comparator Select Register
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 0; // Digital Compare Output A Event 1
EPwm1Regs.TZDCSEL.bit.DCAEVT2 = 0; // Digital Compare Output A Event 2
EPwm1Regs.TZDCSEL.bit.DCBEVT1 = 0; // Digital Compare Output B Event 1
EPwm1Regs.TZDCSEL.bit.DCBEVT2 = 0; // Digital Compare Output B Event 2
*/
EPwm1Regs.TZDCSEL.all = (EPwm1Regs.TZDCSEL.all & ~0xFFF) | 0x0;
/* // Digital Compare Filter Control Register
EPwm1Regs.DCFCTL.bit.BLANKE = 0; // Blanking Enable/Disable
EPwm1Regs.DCFCTL.bit.PULSESEL = 1; // Pulse Select for Blanking & Capture Alignment
EPwm1Regs.DCFCTL.bit.BLANKINV = 0; // Blanking Window Inversion
EPwm1Regs.DCFCTL.bit.SRCSEL = 0; // Filter Block Signal Source Select
*/
EPwm1Regs.DCFCTL.all = (EPwm1Regs.DCFCTL.all & ~0x3F) | 0x10;
EPwm1Regs.DCFOFFSET = 0; // Digital Compare Filter Offset Register
EPwm1Regs.DCFWINDOW = 0; // Digital Compare Filter Window Register
/* // Digital Compare Capture Control Register
EPwm1Regs.DCCAPCTL.bit.CAPE = 0; // Counter Capture Enable
*/
EPwm1Regs.DCCAPCTL.all = (EPwm1Regs.DCCAPCTL.all & ~0x1) | 0x0;
/* // HRPWM Configuration Register
EPwm1Regs.HRCNFG.bit.SWAPAB = 0; // Swap EPWMA and EPWMB Outputs Bit
EPwm1Regs.HRCNFG.bit.SELOUTB = 0; // EPWMB Output Selection Bit
*/
EPwm1Regs.HRCNFG.all = (EPwm1Regs.HRCNFG.all & ~0xA0) | 0x0;
/* Update the Link Registers with the link value for all the Compare values and TBPRD */
/* No error is thrown if the ePWM register exists in the model or not */
EPwm1Regs.EPWMXLINK.bit.TBPRDLINK = 0;
EPwm1Regs.EPWMXLINK.bit.CMPALINK = 0;
EPwm1Regs.EPWMXLINK.bit.CMPBLINK = 0;
EPwm1Regs.EPWMXLINK.bit.CMPCLINK = 0;
EPwm1Regs.EPWMXLINK.bit.CMPDLINK = 0;
/* SYNCPER - Peripheral synchronization output event
EPwm1Regs.HRPCTL.bit.PWMSYNCSEL = 0; // EPWMSYNCPER selection
EPwm1Regs.HRPCTL.bit.PWMSYNCSELX = 0; // EPWMSYNCPER selection
*/
EPwm1Regs.HRPCTL.all = (EPwm1Regs.HRPCTL.all & ~0x72) | 0x0;
EDIS;
EALLOW;
/* Enable TBCLK within the EPWM*/
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
}
/* End of SystemInitialize for S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' */
/* ConstCode for S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' incorporates:
* SubSystem: '<Root>/PI_Controller_ISR'
*/
/* ConstCode for function-call system: '<Root>/PI_Controller_ISR' */
/* Asynchronous task reads absolute time. Data (absolute time)
transfers from low priority task (base rate) to high priority
task (asynchronous rate). Double buffers are used to ensure
data integrity.
-- rtmL2HLastBufWr is the buffer index that is written last.
*/
stab_CL_20khz_M->Timing.clockTick1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTick
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
stab_CL_20khz_M->Timing.clockTickH1 =
stab_CL_20khz_M->Timing.rtmL2HDbBufClockTickH
[stab_CL_20khz_M->Timing.rtmL2HLastBufWr];
/* ConstCode for S-Function (c2802xpwm): '<S1>/ePWM_2' incorporates:
* Constant: '<S1>/Constant4'
*/
EPwm2Regs.TBPHS.bit.TBPHS = 5000.0;
/* End of ConstCode for S-Function (c28xisr_c2000): '<Root>/C28x Hardware Interrupt1' */
}
/*
* File trailer for generated code.
*
* [EOF]
*/
