Part Number: LAUNCHXL-F280049C
Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi Team,
I am trying to configure DAC channel B and verify the output using ADC. I have configured it to use internal bandgap voltage of 3.3V. I was able to successfully test using DAC-A and ADCINA0. However, with DAC channel B and ADCINA1, when I change the DAC input, there is no change in the ADC output.
PFA, the code and below are the register values.
I would like to know if any setting is missing because with similar settings for DAC-A, I was able to changes in ADCINA0 when i changed the input to DAC. However, with DAC-B, the value is fixed around 4k.
//
// Included Files
//
#include "F28x_Project.h"
//
// Defines
//
#define RESULTS_BUFFER_SIZE 256
#define REFERENCE_VDAC 0
#define REFERENCE_VREF 1
#define DACA 1
#define DACB 2
#define REFERENCE REFERENCE_VREF
#define DAC_NUM DACB
//
// Globals
//
uint16_t adcAResults[RESULTS_BUFFER_SIZE]; // Buffer for results
uint16_t index; // Index into result buffer
volatile uint16_t bufferFull; // Flag to indicate buffer is full
volatile struct DAC_REGS* DAC_PTR[3] = {0x0,&DacaRegs,&DacbRegs};
uint16_t dacval = 2048;
//
// Function Prototypes
//
void initADC(void);
void initEPWM(void);
void initADCSOC(void);
__interrupt void adcA1ISR(void);
void configureDAC(uint16_t dac_num);
//
// Main
//
void main(void)
{
//
// Initialize device clock and peripherals
//
InitSysCtrl();
//
// Initialize GPIO
//
InitGpio();
//
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
//
InitPieVectTable();
//
// Map ISR functions
//
EALLOW;
PieVectTable.ADCA1_INT = &adcA1ISR; // Function for ADCA interrupt 1
EDIS;
//
// Configure the ADC and power it up
//
initADC();
//
// Configure the ePWM
//
initEPWM();
//
// Setup the ADC for ePWM triggered conversions on channel 1
//
initADCSOC();
configureDAC(DAC_NUM);
//
// Enable global Interrupts and higher priority real-time debug events:
//
IER |= M_INT1; // Enable group 1 interrupts
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Initialize results buffer
//
for(index = 0; index < RESULTS_BUFFER_SIZE; index++)
{
adcAResults[index] = 0;
}
index = 0;
bufferFull = 0;
//
// Enable PIE interrupt
//
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
//
// Sync ePWM
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;
//
// Take conversions indefinitely in loop
//
while(1)
{
//
// Start ePWM
//
EPwm1Regs.ETSEL.bit.SOCAEN = 1; // Enable SOCA
EPwm1Regs.TBCTL.bit.CTRMODE = 0; // Unfreeze, and enter up count mode
DAC_PTR[DAC_NUM]->DACVALS.all = dacval;
DELAY_US(2);
//
// Wait while ePWM causes ADC conversions, which then cause interrupts,
// which fill the results buffer, eventually setting the bufferFull
// flag
//
while(!bufferFull)
{
}
bufferFull = 0; //clear the buffer full flag
//
// Stop ePWM
//
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOCA
EPwm1Regs.TBCTL.bit.CTRMODE = 3; // Freeze counter
}
}
//
// initADC - Function to configure and power up ADCA.
//
void initADC(void)
{
//
// Setup VREF as internal
//
SetVREF(ADC_ADCA, ADC_INTERNAL, 1);
SetVREF(ADC_ADCB, ADC_INTERNAL, ADC_VREF3P3);
EALLOW;
//
// Set ADCCLK divider to /4
//
AdcaRegs.ADCCTL2.bit.PRESCALE = 6;
//
// Set pulse positions to late
//
AdcaRegs.ADCCTL1.bit.INTPULSEPOS = 1;
//
// Power up the ADC and then delay for 1 ms
//
AdcaRegs.ADCCTL1.bit.ADCPWDNZ = 1;
EDIS;
DELAY_US(1000);
}
//
// initEPWM - Function to configure ePWM1 to generate the SOC.
//
void initEPWM(void)
{
EALLOW;
EPwm1Regs.ETSEL.bit.SOCAEN = 0; // Disable SOC on A group
EPwm1Regs.ETSEL.bit.SOCASEL = 4; // Select SOC on up-count
EPwm1Regs.ETPS.bit.SOCAPRD = 1; // Generate pulse on 1st event
EPwm1Regs.CMPA.bit.CMPA = 0x0800; // Set compare A value to 2048 counts
EPwm1Regs.TBPRD = 0x1000; // Set period to 4096 counts
EPwm1Regs.TBCTL.bit.CTRMODE = 3; // Freeze counter
EDIS;
}
//
// initADCSOC - Function to configure ADCA's SOC0 to be triggered by ePWM1.
//
void initADCSOC(void)
{
//
// Select the channels to convert and the end of conversion flag
//
EALLOW;
AdcaRegs.ADCSOC0CTL.bit.CHSEL = 1; // SOC0 will convert pin A1
// 0:A0 1:A1 2:A2 3:A3
// 4:A4 5:A5 6:A6 7:A7
// 8:A8 9:A9 A:A10 B:A11
// C:A12 D:A13 E:A14 F:A15
AdcaRegs.ADCSOC0CTL.bit.ACQPS = 9; // Sample window is 10 SYSCLK cycles
AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5; // Trigger on ePWM1 SOCA
AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; // Make sure INT1 flag is cleared
EDIS;
}
void configureDAC(uint16_t dac_num)
{
EALLOW;
DAC_PTR[dac_num]->DACCTL.bit.DACREFSEL = REFERENCE;
DAC_PTR[dac_num]->DACCTL.bit.MODE = 1;
DAC_PTR[dac_num]->DACOUTEN.bit.DACOUTEN = 1;
DAC_PTR[dac_num]->DACVALS.all = 0;
DELAY_US(10); // Delay for buffered DAC to power up
EDIS;
}
//
// adcA1ISR - ADC A Interrupt 1 ISR
//
__interrupt void adcA1ISR(void)
{
//
// Add the latest result to the buffer
// ADCRESULT0 is the result register of SOC0
adcAResults[index++] = AdcaResultRegs.ADCRESULT0;
//
// Set the bufferFull flag if the buffer is full
//
if(RESULTS_BUFFER_SIZE <= index)
{
index = 0;
bufferFull = 1;
}
//
// Clear the interrupt flag
//
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1;
//
// Check if overflow has occurred
//
if(1 == AdcaRegs.ADCINTOVF.bit.ADCINT1)
{
AdcaRegs.ADCINTOVFCLR.bit.ADCINT1 = 1; //clear INT1 overflow flag
AdcaRegs.ADCINTFLGCLR.bit.ADCINT1 = 1; //clear INT1 flag
}
//
// Acknowledge the interrupt
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
