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TMS320F280049: Maximum interrupt latency

Hitoshi Sugawara
Mastermind 20440 points

Part Number: TMS320F280049

Hi Experts,

According to the TRM

The minimum interrupt latency is 14 SYSCLK cycles in  "3.5.3 Interrupt Entry Sequence."

Could you please let me know how to estimate the maximum interrupt latency clocks?

Thank you for your help.
Best regards,
Hitoshi

  • 0
    TI__Mastermind 27055 points

    Hitoshi-san,

    Unlike minimum interrupt latency, I don't know that we can quantify maximum interrupt latency. I have assigned the issue to an expert for comment.

    Thanks,

    Sira

  • 0 in reply to Sira Rao80
    TI__Mastermind 27055 points

    Feedback from Architect, will also assign to Design expert for comment.

    It is hard to bound the maximum interrupt entry time since it could be blocked by some software that is setting INTM. 

    The other thing that can delay the interrupt entry is a wait-stated memory access (either program or data). 

    Both of the above are dependent on what the CPU is executing and from where. Given that, one cannot bound or put a max since it is also dependent on user code. 

  • 0 in reply to Sira Rao80
    TI__Prodigy 30 points

    Hi Hitoshi, Sira,

    If there is no interrupt pending currently, then PIE will generate interrupt to CPU immediately (same cycle) after receiving an interrupt from a peripheral.  Priority order of PIE is as given below which is captured in TRM. (Section-3.5.5)

         

    Internal to CPU ISR latency (14 to 16 cycles) is explained in below article.

       https://processors.wiki.ti.com/index.php/Interrupt_FAQ_for_C2000

     

    The question is mainly related to CPU servicing ISR after receiving an interrupt. Please refer to ISR Latency section provided in above reference. Best case (min latency) is 14 cycles. Worst case depends on current CPU instruction (Interruptable or non-interruptible) and other factors described in the section.  Instructions (interruptable vs non-interruptable) are described in C28 CPU instruction reference guide. Considering these parameters we can calculate the worst case latency on case by case basis. Hope this information helps.

    Best regards,

    Arif

     

     

  • 0 in reply to Mohammed Arif
    TI__Mastermind 20440 points

    Hi Arif and Sira,

    Thank you so much for the detailed information.
    The WiKi helps me a lot.
    Now I clearly understood what spends cycles.

    Best regards,
    Hitoshi